公开(公告)号：US06433985B1

公开(公告)日：2002-08-13

申请号：US09476244

申请日：1999-12-30

申请人： Steven H. Voldman ,  Richard Q. Williams

发明人： Steven H. Voldman ,  Richard Q. Williams

IPC分类号： H02H322

CPC分类号： H01L27/0251 ,  H02H9/046

摘要： An ESD protection network is described which prevents high voltage oxide stress. The network consists of a filter network (such as a blocking capacitor) and diode protection elements. The filter network can be designed for several types of ESD protection functions. It can be designed to provide voltage reduction for ESD pulses, and to selectively block the frequency components of ESD pulses.

摘要翻译： 描述了ESD保护网络，其防止高电压氧化物应力。 网络由滤波网络（如隔离电容器）和二极管保护元件组成。 滤波器网络可以设计用于几种类型的ESD保护功能。 它可以设计用于为ESD脉冲提供电压降低，并有选择地阻断ESD脉冲的频率分量。

公开(公告)号：US08392867B2

公开(公告)日：2013-03-05

申请号：US13005599

申请日：2011-01-13

申请人： Yanqing Deng ,  Paul A. Hyde ,  James M. Johnson ,  Todd G. McKenzie ,  Scott K. Springer ,  Richard Q. Williams

发明人： Yanqing Deng ,  Paul A. Hyde ,  James M. Johnson ,  Todd G. McKenzie ,  Scott K. Springer ,  Richard Q. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A system and method for developing condensed netlists for sub-circuits within an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists rather than full netlists. An IC layout is segmented into a plurality of sub-circuits, each comprising a group of one or more of a given type of active devices connected to (i.e., sharing) the same electrical sub-circuit terminals through a similar resistive network (i.e. such that they are subjected to approximately the same overall combined parasitic resistances). Full netlists corresponding to the sub-circuits are extracted from the layout and condensed. Each condensed netlist accounts for performance variations (e.g., as a function of variations in operating power supply voltages, operating temperatures and, optionally, self-heating and/or stress) exhibited by the active devices and resistive network in a sub-circuit. The condensed netlists for the sub-circuits are then simulated over the full range of operating temperatures and full range of operating power supply voltages for the integrated circuit in order to generate a performance model for the integrated circuit.

摘要翻译： 一种用于开发集成电路内的子电路的精简网表的系统和方法，以及基于精简网表而不是完整的网表来对集成电路的性能进行建模。 IC布局被分割成多个子电路，每个子电路包括通过类似的电阻网络连接到（即共享）相同的电子电路终端的给定类型的有源设备中的一个或多个的组 它们受到大致相同的总体组合寄生电阻）。 从布局中提取与子电路对应的完整网表，并进行浓缩。 每个浓缩网表列出了子电路中的有源器件和电阻网络所呈现的性能变化（例如，作为工作电源电压，工作温度以及任选的自发热和/或应力的变化的函数）。 然后在集成电路的工作温度和工作电源电压的全范围内模拟子电路的精简网表，以便为集成电路生成性能模型。

公开(公告)号：US20120235233A1

公开(公告)日：2012-09-20

申请号：US13046902

申请日：2011-03-14

申请人： Edward J. Nowak ,  Richard Q. Williams

发明人： Edward J. Nowak ,  Richard Q. Williams

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

摘要： The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.

摘要翻译： 本公开一般涉及金属氧化物半导体场效应晶体管（MOSFET）结构及其形成方法。 MOSFET结构在衬底上包括至少一个半导体本体; 在所述至少一个半导体主体的顶表面上的电介质盖，其中所述至少一个半导体本体的宽度小于所述电介质盖的宽度; 保护地涂覆所述至少一个半导体主体的栅介质层; 以及栅极电介质层上的至少一个导电栅极。

公开(公告)号：US08211741B2

公开(公告)日：2012-07-03

申请号：US13170525

申请日：2011-06-28

申请人： Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

发明人： Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

IPC分类号： H01L51/00

CPC分类号： H01L51/0541 ,  B82Y10/00 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/75 ,  Y10S977/751 ,  Y10S977/752

摘要： Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.

摘要翻译： 在半导体碳纳米管上形成栅电极，然后根据一维电路布局的图案在碳纳米管上沉积和图案化空穴诱导材料层和电子诱导材料层。 可以通过切割碳纳米管的一部分来形成电气隔离，形成空穴诱导区域和碳纳米管的电子诱导区域的反向偏置接合点，或者通过电介质层对两个器件区域之间的电介质层进行电偏置 碳纳米管。 碳纳米管可以被布置为使得可以将空穴诱导材料层和电子诱导材料层分配给每个碳纳米管以形成诸如静态随机存取存储器（SRAM）阵列的周期性结构。

公开(公告)号：US20120054711A1

公开(公告)日：2012-03-01

申请号：US12873554

申请日：2010-09-01

申请人： Dureseti Chidambarrao ,  Richard Q. Williams

发明人： Dureseti Chidambarrao ,  Richard Q. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A method (and computer program) identify shapes and locations of transistor elements within a geometric circuit layout. The transistor elements include an active area, at least one gate conductor and other transistor elements. Also, the gate conductor has sides running in a first direction, and has a width dimension running in a second direction perpendicular to the first direction. The method defines regions within the geometric circuit layout. To do so, the method defines a first region having a perimeter positioned along the sides of the gate conductor where the gate conductor intersects the active area and then expands the perimeter of the first region in the second direction to edges of the active area to define a perimeter of a second region. The first region and the second share perimeters in the first direction. The method then expands the perimeter of the second region in the first direction to define a perimeter of a third region. The second region and the third region share perimeters in the second direction. The method then separately evaluates effects the other transistor elements have within each of the first region, the second region, and the third region, to determine a characteristic of the gate conductor.

摘要翻译： 方法（和计算机程序）识别晶体管元件在几何电路布局内的形状和位置。 晶体管元件包括有源区，至少一个栅极导体和其它晶体管元件。 此外，栅极导体具有沿第一方向延伸的侧面，并且具有沿与第一方向垂直的第二方向延伸的宽度尺寸。 该方法定义几何电路布局内的区域。 为此，该方法限定了具有沿着栅极导体的侧面定位的周边的第一区域，其中栅极导体与有源区域相交，然后在第二方向上将第一区域的周边扩展到有源区域的边缘，以限定 第二区域的周边。 第一个区域和第二个共享周边的第一个方向。 该方法然后在第一方向上扩展第二区域的周边以限定第三区域的周长。 第二区域和第三区域在第二方向共享周边。 该方法然后分别评估其它晶体管元件在第一区域，第二区域和第三区域内的效应，以确定栅极导体的特性。

公开(公告)号：US08017934B2

公开(公告)日：2011-09-13

申请号：US12850259

申请日：2010-08-04

申请人： Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

发明人： Joerg Appenzeller ,  AJ Kleinosowski ,  Edward J. Nowak ,  Richard Q. Williams

IPC分类号： H01L51/00

CPC分类号： H01L51/0541 ,  B82Y10/00 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/75 ,  Y10S977/751 ,  Y10S977/752

摘要： Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.

摘要翻译： 在半导体碳纳米管上形成栅电极，然后根据一维电路布局的图案在碳纳米管上沉积和图案化空穴诱导材料层和电子诱导材料层。 可以通过切割碳纳米管的一部分来形成电气隔离，形成空穴诱导区域和碳纳米管的电子诱导区域的反向偏置接合点，或者通过介电层在两个器件区域之间电气偏置区域 碳纳米管。 碳纳米管可以被布置为使得可以将空穴诱导材料层和电子诱导材料层分配给每个碳纳米管以形成诸如静态随机存取存储器（SRAM）阵列的周期性结构。

公开(公告)号：US07986022B2

公开(公告)日：2011-07-26

申请号：US12621956

申请日：2009-11-19

申请人： Kangguo Cheng ,  Toshiharu Furukawa ,  Robert R. Robison ,  William R. Tonti ,  Richard Q. Williams

发明人： Kangguo Cheng ,  Toshiharu Furukawa ,  Robert R. Robison ,  William R. Tonti ,  Richard Q. Williams

IPC分类号： H01L31/105

CPC分类号： H01L31/03529 ,  H01L27/14643 ,  H01L29/0657 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66234 ,  H01L29/732 ,  H01L29/8611 ,  H01L29/868 ,  H01L31/0352 ,  H01L31/103 ,  Y02E10/50

摘要： A diode comprises a substrate formed of a first material having a first doping polarity. The substrate has a planar surface and at least one semispherical structure extending from the planar surface. The semispherical structure is formed of the first material. A layer of second material is over the semispherical structure. The second material comprises a second doping polarity opposite the first doping polarity. The layer of second material conforms to the shape of the semispherical structure. A first electrical contact is connected to the substrate, and a second electrical contact is connected to the layer of second material. Additional semiconductor structures are formed by fabricating additional layers over the original layers.

摘要翻译： 二极管包括由具有第一掺杂极性的第一材料形成的衬底。 衬底具有平坦表面和从平面表面延伸的至少一个半球形结构。 半球形结构由第一材料形成。 第二材料层在半球形结构之上。 第二材料包括与第一掺杂极性相反的第二掺杂极性。 第二材料层符合半球形结构的形状。 第一电触头连接到基板，第二电触点连接到第二材料层。 通过在原始层上制造附加层来形成附加的半导体结构。

公开(公告)号：US07934181B2

公开(公告)日：2011-04-26

申请号：US12130472

申请日：2008-05-30

申请人： Hussein I. Hanafi ,  Richard Q. Williams

发明人： Hussein I. Hanafi ,  Richard Q. Williams

IPC分类号： G06F17/50 ,  G11C16/06 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/02 ,  G11C8/08 ,  G11C11/413

摘要： The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.

摘要翻译： 本发明涉及通过使用增强字线来提高静态随机存取存储器（SRAM）单元的稳定性的方法和装置。 具体地说，将升压的字线电压（Vdd'）施加到所选择的SRAM单元的字线，而这样的升压字线电压（Vdd'）比SRAM单元的电源电压（Vdd）充分高 以将细胞稳定性提高到所需水平。 具体地，通过使用例如BERKELEY-SPICE仿真程序的电路仿真程序，基于特定单元配置为每个SRAM单元预定特定的升压字线电压。 然后使用升压电压发生器将预定的升压字线电压施加到所选择的SRAM单元。

公开(公告)号：US07818692B2

公开(公告)日：2010-10-19

申请号：US11946937

申请日：2007-11-29

申请人： Dureseti Chidambarrao ,  Jason Hibbeler ,  Richard Q. Williams

发明人： Dureseti Chidambarrao ,  Jason Hibbeler ,  Richard Q. Williams

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5081

摘要： A method of improving a circuit design for a very large scale integrated circuit is provided which represents a plurality of semiconductor devices interconnected in a circuit. It is determined whether an edge of a feature of one of the plurality of semiconductor devices in the design can be moved in a first direction by a distance within a permitted range, such that a performance goal and a matching goal for the circuit are served. If so, the edge is moved in the first direction by the distance calculated to best serve the performance goal and the matching goal. The foregoing steps may be repeated for each of the plurality of semiconductor devices. If necessary, the foregoing steps may be repeated until the performance goal and matching goal for the circuit are deemed to be adequately served.

摘要翻译： 提供了一种改进用于大规模集成电路的电路设计的方法，其表示在电路中互连的多个半导体器件。 确定设计中的多个半导体器件中的一个的特征的边缘是否可以在第一方向上移动允许范围内的距离，使得提供电路的性能目标和匹配目标。 如果是这样，边缘沿第一个方向移动计算的距离，以最佳地满足性能目标和匹配目标。 对于多个半导体器件中的每一个可以重复上述步骤。 如果需要，可以重复上述步骤，直到电路的性能目标和匹配目标被认为是充分的。

公开(公告)号：US07761278B2

公开(公告)日：2010-07-20

申请号：US11673824

申请日：2007-02-12

申请人： Dureseti Chidambarrao ,  Richard Q. Williams

发明人： Dureseti Chidambarrao ,  Richard Q. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F17/5068 ,  G06F2217/16

摘要： A computational methodology that improves the accuracy of model parameters in a compact model uses methods and algorithms to self-consistently match independently developed base and stress models by re-fitting the stress model to the data set that generates the base model. The re-fitting algorithm removes any discrepancy between the base model and the stress model as the stress model is applied to the data set obtained from a dimension-scaling macro. Stress offsets for dimension-scaling macro devices are calculated to fit the measured values of the model parameters for the same devices. The process of fitting the model parameters to the data set from the dimension-scaling macro calculates constant, linear, and quadratic coefficients for the model parameters, which are employed to increase the accuracy of the model parameters and of the compact model used in circuit simulations and optimization.

摘要翻译： 提高紧凑型模型中模型参数精度的计算方法使用方法和算法通过将应力模型重新拟合到生成基本模型的数据集来自主统一地匹配独立开发的基础和应力模型。 随着应力模型应用于从尺寸缩放宏获取的数据集，重新拟合算法消除了基本模型和应力模型之间的任何差异。 计算尺寸缩放宏设备的应力偏移量，以适应​​相同设备的模型参数的测量值。 将模型参数从维度缩放宏拟合到数据集的过程计算模型参数的常数，线性和二次系数，这些系数用于提高模型参数的精度和电路模拟中使用的紧凑模型 和优化。