公开(公告)号：US08907420B2

公开(公告)日：2014-12-09

申请号：US12789008

申请日：2010-05-27

申请人： Wataru Saito ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

发明人： Wataru Saito ,  Syotaro Ono ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/94 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof.

摘要翻译： 功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和形成在第一半导体层上的第二导电类型的第三半导体层，并且沿着平行于第一半导体层的表面的至少一个方向交替布置; 第一主电极; 选择性地形成在第二半导体层的表面和第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地形成在第四半导体层的表面中的第一导电类型的第五半导体层; 第二主电极; 和控制电极。 第二和第三半导体层中的至少一个具有沿着一个方向的掺杂剂浓度分布，掺杂剂浓度分布在其两端以外的位置处具有局部最小值。

公开(公告)号：US08872261B2

公开(公告)日：2014-10-28

申请号：US13607255

申请日：2012-09-07

申请人： Hiroyuki Irifune ,  Wataru Saito ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Hiroshi Ohta ,  Junji Suzuki

发明人： Hiroyuki Irifune ,  Wataru Saito ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Hiroshi Ohta ,  Junji Suzuki

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7811

摘要： A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third diffusion layers are the same.

摘要翻译： 半导体器件包括各自具有多个扩散层的第一，第二和第三半导体层。 第一扩散层的第一方向宽度是相同的。 第一扩散层内的杂质量从第一半导体层的底端向顶端逐渐增加。 第二扩散层的第一方向宽度相同。 第二扩散层内的杂质量相同。 第三扩散层的第一方向宽度比第一扩散层的第一方向宽度和第二扩散层的第一方向宽度在相同水平处窄，并且从第一扩散层的第一方向宽度逐渐变窄到 第三半导体层。 第三扩散层内的杂质量相同。

公开(公告)号：US08816410B2

公开(公告)日：2014-08-26

申请号：US13357381

申请日：2012-01-24

申请人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/772

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7395

摘要： A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.

摘要翻译： 实施例的第一半导体器件包括第一导电类型的第一半导体层，第一控制电极，引出电极，第二控制电极和第三控制电极。 第一控制电极通过第一绝缘膜面对第一导电类型的第二半导体层，第二导电类型的第三半导体层和第一导电类型的第四半导体层。 第二控制电极和第三控制电极通过第二绝缘膜电连接到引出电极，并且与提取电极下方的第二半导体层相对。 第二控制电极和整个第三控制电极的至少一部分设置在引出电极的下方。 第二控制电极的电阻高于第三控制电极的电阻。

公开(公告)号：US08592893B2

公开(公告)日：2013-11-26

申请号：US13052893

申请日：2011-03-21

申请人： Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Shunji Taniuchi ,  Miho Watanabe

发明人： Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Shunji Taniuchi ,  Miho Watanabe

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/408 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66734 ,  H01L29/7811

摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type, a fourth semiconductor layer, a fifth semiconductor layer, a first and second main electrode, a first and second insulating film and a control electrode. The second and third layers are provided periodically on the first layer. The fourth layer is provided on the third layer. The fifth layer is selectively provided on the fourth layer. The first film is provided on sidewalls of a trench that reaches from a surface of the fifth layer to the second layer. The second film is provided closer to a bottom side of the trench than the first film and has a higher permittivity than the first film. The control electrode is embedded in the trench.

摘要翻译： 根据一个实施例，功率半导体器件包括第一导电类型的第一半导体层，第一导电类型的第二半导体层和第二导电类型的第三半导体层，第四半导体层，第五半导体层， 第一和第二主电极，第一和第二绝缘膜和控制电极。 第二层和第三层周期性地设置在第一层上。 第四层设置在第三层上。 第五层选择性地设置在第四层上。 第一膜设置在从第五层的表面到第二层的沟槽的侧壁上。 第二膜比第一膜更靠近沟槽的底侧，并且具有比第一膜更高的介电常数。 控制电极嵌入沟槽中。

公开(公告)号：US08431992B2

公开(公告)日：2013-04-30

申请号：US13023210

申请日：2011-02-08

申请人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

发明人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

公开(公告)号：US20130069158A1

公开(公告)日：2013-03-21

申请号：US13425258

申请日：2012-03-20

申请人： Hiroshi OHTA ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Junji Suzuki ,  Hiroyuki Irifune ,  Wataru Saito

发明人： Hiroshi OHTA ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Junji Suzuki ,  Hiroyuki Irifune ,  Wataru Saito

IPC分类号： H01L29/78

CPC分类号： H01L29/0623 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811

摘要： A power semiconductor device includes a high resistance epitaxial layer having a first pillar region and a second pillar region as a drift layer. The first pillar region includes a plurality of first pillars of the first conductivity type and a plurality of second pillars of the second conductivity type disposed alternately along a first direction. The second pillar region is adjacent to the first pillar region along the first direction. The second pillar region includes a third pillar and a fourth pillar of a conductivity type opposite to a conductivity type of the third pillar. A net quantity of impurities in the third pillar is less than a net quantity of impurities in each of the plurality of first pillars. A net quantity of impurities in the fourth pillar is less than the net quantity of impurities in the third pillar.

摘要翻译： 功率半导体器件包括具有第一柱区和第二柱区作为漂移层的高电阻外延层。 第一支柱区域包括多个第一导电类型的第一支柱和沿着第一方向交替布置的多个第二导电类型的第二支柱。 第二柱区域沿着第一方向与第一柱状区域相邻。 第二柱区域包括与第三柱的导电类型相反的导电类型的第三柱和第四柱。 第三支柱中的杂质净量少于多个第一支柱中的每一个中的杂质的净量。 第四柱中净杂质量少于第三柱中杂质的净量。

公开(公告)号：US20110133278A1

公开(公告)日：2011-06-09

申请号：US13023210

申请日：2011-02-08

申请人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

发明人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

公开(公告)号：US07737467B2

公开(公告)日：2010-06-15

申请号：US11507598

申请日：2006-08-22

申请人： Wataru Saito ,  Masaaki Onomura

发明人： Wataru Saito ,  Masaaki Onomura

IPC分类号： H01L31/0304

CPC分类号： H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404

摘要： A nitride semiconductor device comprises: a laminated body; a first and second main electrode provided in a second and third region, respectively, adjacent to either end of the first region on the major surface of the laminated body; and a third main electrode. The laminated body includes a first semiconductor layer of a nitride semiconductor and a second semiconductor layer of a nondoped or n-type nitride semiconductor having a wider bandgap than the first semiconductor layer, the second semiconductor layer being provided on the first semiconductor layer. The third main electrode is provided on the major surface of the laminated body and opposite to the control electrode across the second main electrode.

摘要翻译： 氮化物半导体器件包括：层叠体; 第一和第二主电极分别设置在第二和第三区域中，邻近层压体的主表面上的第一区域的任一端; 和第三主电极。 层叠体包括氮化物半导体的第一半导体层和具有比第一半导体层更宽的带隙的非掺杂或n型氮化物半导体的第二半导体层，第二半导体层设置在第一半导体层上。 第三主电极设置在层叠体的主表面上，并与第二主电极相对的控制电极相对。

公开(公告)号：US20090302373A1

公开(公告)日：2009-12-10

申请号：US12543165

申请日：2009-08-18

申请人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

发明人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

公开(公告)号：US07541643B2

公开(公告)日：2009-06-02

申请号：US11399448

申请日：2006-04-07

申请人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi

发明人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7811

摘要： This semiconductor device comprises a pillar layer including a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type formed alternately on a first semiconductor layer. At the same depth position in the device region and the end region, a difference between an impurity concentration [cm-3] of the second semiconductor pillar layer in the device region and that of the second semiconductor pillar layer in the end region is less than plus or minus 5%. A width W11 [um] of the first semiconductor pillar layer in the device region, a width W21 [um] of the second semiconductor pillar layer in the device region, a width W12 [um] of the first semiconductor pillar layer in the end region, and a width W22 [um] of the second semiconductor pillar layer in the end region, meet the relationship of W21/W11

摘要翻译： 该半导体器件包括：交替地在第一半导体层上形成的包括第一导电类型的第一半导体柱层和第二导电类型的第二半导体柱层的柱层。 在器件区域和端部区域的相同深度位置处，器件区域中的第二半导体柱层的杂质浓度[cm-3]与末端区域中的第二半导体柱层的杂质浓度[cm-3]之间的差小于 加或减5％。 器件区域中的第一半导体柱层的宽度W11 [μm]，器件区域中的第二半导体柱层的宽度W21 [μm]，端部区域中的第一半导体柱层的宽度W12 [μm] ，并且端部区域中的第二半导体柱层的宽度W22 [μm]满足W21 / W11