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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20100258854A1

    公开(公告)日：2010-10-14

    申请号：US12821708

    申请日：2010-06-23

    申请人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

    发明人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

    IPC分类号： H01L27/088

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

    摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

    摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

    Semiconductor device including first and second semiconductor regions with increasing impurity concentrations from a substrate surface
    2.
    发明授权
    Semiconductor device including first and second semiconductor regions with increasing impurity concentrations from a substrate surface 有权
    半导体器件包括从衬底表面增加杂质浓度的第一和第二半导体区域

    公开(公告)号：US08431992B2

    公开(公告)日：2013-04-30

    申请号：US13023210

    申请日：2011-02-08

    申请人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

    发明人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

    摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

    摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110133278A1

    公开(公告)日：2011-06-09

    申请号：US13023210

    申请日：2011-02-08

    申请人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

    发明人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

    摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

    摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20090302373A1

    公开(公告)日：2009-12-10

    申请号：US12543165

    申请日：2009-08-18

    申请人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

    发明人： Kenichi TOKANO ,  Tetsuo Matsuda ,  Wataru Saito

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

    摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

    摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

    Semiconductor device with tapered trenches and impurity concentration gradients
    5.
    发明授权
    Semiconductor device with tapered trenches and impurity concentration gradients 有权
    具有锥形沟槽和杂质浓度梯度的半导体器件

    公开(公告)号：US07898031B2

    公开(公告)日：2011-03-01

    申请号：US12821708

    申请日：2010-06-23

    申请人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

    发明人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

    IPC分类号： H01L29/772

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

    摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

    摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

    Power semiconductor device with epitaxially-filled trenches
    6.
    发明授权
    Power semiconductor device with epitaxially-filled trenches 有权
    具有外延填充沟槽的功率半导体器件

    公开(公告)号：US07595530B2

    公开(公告)日：2009-09-29

    申请号：US11364203

    申请日：2006-03-01

    申请人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

    发明人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

    IPC分类号： H01L29/38

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

    摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

    摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

    Semiconductor device having trenches filled with a semiconductor having an impurity concentration gradient
    7.
    发明授权
    Semiconductor device having trenches filled with a semiconductor having an impurity concentration gradient 有权
    具有填充有具有杂质浓度梯度的半导体的沟槽的半导体器件

    公开(公告)号：US07936015B2

    公开(公告)日：2011-05-03

    申请号：US12543165

    申请日：2009-08-18

    申请人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

    发明人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

    IPC分类号： H01L29/772

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

    摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

    摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

    Semiconductor device
    8.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060197152A1

    公开(公告)日：2006-09-07

    申请号：US11364203

    申请日：2006-03-01

    申请人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

    发明人： Kenichi Tokano ,  Tetsuo Matsuda ,  Wataru Saito

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

    摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

    摘要翻译： 第一导电类型的单晶半导体层设置在半导体衬底的表面上。 在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。 外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。 多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

    Plating method
    10.
    发明授权
    Plating method 失效
    电镀方法

    公开(公告)号：US07575664B2

    公开(公告)日：2009-08-18

    申请号：US11135328

    申请日：2005-05-24

    申请人： Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

    发明人： Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

    IPC分类号： C25D21/12

    CPC分类号： C25D5/16 ,  C25D5/02 ,  C25D5/06 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

    摘要： A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.

    摘要翻译： 对形成在具有凹陷图案的基板上的导电层施加阴极电位。 将与阳极电接触的电镀溶液供给到导电层，以在导电层上形成镀膜。 此时，通过使包含电镀液的浸渍部件面对导电层而供给电镀液。 由于电镀溶液滞留在凹陷中，所以与基板的上表面相比，供给电镀液的量较多，因此抑制了镀膜的镀覆速度。 因此，可以在诸如凹槽或孔的凹陷中优先地形成镀膜。