公开(公告)号：US20060252227A1

公开(公告)日：2006-11-09

申请号：US11486889

申请日：2006-07-13

Applicant: Wen-Chin Lee ,  Yee-Chia Yeo

Inventor： Wen-Chin Lee ,  Yee-Chia Yeo

IPC: H01L21/76

CPC classification number: H01L27/11 ,  H01L27/1104

Abstract: A semiconductor device comprises a substrate. In addition, the semiconductor device comprises an active region and an isolation region. The active region is in the substrate and comprises a semiconductor material. The isolation region is also in the substrate, adjacent the active region and comprises an insulating material. The active region and isolation region form a surface having a step therein. The semiconductor further comprises a dielectric material formed over the step. The dielectric material has a dielectric constant greater than about 8.

Abstract translation: 半导体器件包括衬底。 此外，半导体器件包括有源区和隔离区。 有源区在衬底中并且包括半导体材料。 隔离区也在衬底中，邻近有源区并且包括绝缘材料。 有源区和隔离区形成其中具有台阶的表面。 半导体还包括在该步骤上形成的电介质材料。 电介质材料的介电常数大于约8。

公开(公告)号：US07112483B2

公开(公告)日：2006-09-26

申请号：US10831021

申请日：2004-04-23

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

IPC: H01L21/8238 ,  H01L21/44

CPC classification number: H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78648

Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

Abstract translation: 提供一种半导体器件及其制造方法。 该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。 第一硅化物可能与第二硅化物不同。 第一硅化物和第二硅化物可以是合金硅化物。

公开(公告)号：US20060109246A1

公开(公告)日：2006-05-25

申请号：US10991419

申请日：2004-11-19

Applicant: Wen-Chin Lee ,  Hsiang-Kuang Chen

Inventor： Wen-Chin Lee ,  Hsiang-Kuang Chen

IPC: G09G5/08

CPC classification number: G06F3/0383 ,  G01D5/145 ,  G06F3/0362

Abstract: An oscillation and rotation metric controller comprised of a scrolling wheel mechanism to oscillate for driving magnetic poles of a permanent magnet to displace thus to generate signals of changed magnetic field, signals being retrieved to achieve lateral oscillation metric control; and a knob switch encoder being fixed to the scrolling wheel mechanism to execute metric control by rotation displacement.

Abstract translation: 振荡和旋转度量控制器包括滚动轮机构，用于振荡以驱动永磁体的磁极，从而移位，从而产生改变的磁场的信号;检索信号以实现横向振荡度量控制; 以及旋钮开关编码器，其被固定到滚动轮机构，以通过旋转位移执行度量控制。

公开(公告)号：US07045847B2

公开(公告)日：2006-05-16

申请号：US10832020

申请日：2004-04-26

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Ye-Chia Yeng

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Ye-Chia Yeng

IPC: H01L27/108

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

Abstract translation: 集成电路包括衬底，第一晶体管和第二晶体管。 第一晶体管具有位于第一栅电极和衬底之间的第一栅电介质部分。 第一栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 第二晶体管具有位于第二栅电极和衬底之间的第二栅介质部分。 第二栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度可以不同于第一等效氧化硅厚度。

公开(公告)号：US20050285140A1

公开(公告)日：2005-12-29

申请号：US10875141

申请日：2004-06-23

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC: H01L21/762 ,  H01L21/8238 ,  H01L29/10 ,  H01L31/0328

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/7846 ,  H01L29/7848

Abstract: A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

Abstract translation: 公开了用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。 在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。 含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。

公开(公告)号：US20050252443A1

公开(公告)日：2005-11-17

申请号：US10847099

申请日：2004-05-17

Applicant: Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

Inventor： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC: C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract translation: 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US20050243210A1

公开(公告)日：2005-11-03

申请号：US10709984

申请日：2004-06-10

Applicant: Wen-Chin Lee

Inventor： Wen-Chin Lee

IPC: H04N5/445

CPC classification number: H04N5/44513 ,  H04N21/42646 ,  H04N21/4884

Abstract: A display system embedded in a media player has an on-screen display (OSD) function for displaying an operation status of the player. When the player obtains a medium signal and outputs a video signal within the medium signal to a screen for displaying video, the invention utilizes software-parsing to parse a subtitle signal within the medium signal, and obtains a text signal within the subtitle signal. Then the subtitle text can be displayed as OSD text using the OSD function of the player.

Abstract translation: 嵌入在媒体播放器中的显示系统具有用于显示播放器的操作状态的屏幕显示（OSD）功能。 当播放器获得媒体信号并将媒体信号中的视频信号输出到用于显示视频的屏幕时，本发明利用软件解析来解析媒体信号内的字幕信号，并获得字幕信号内的文本信号。 然后，使用播放器的OSD功能，字幕文本可以显示为OSD文本。

公开(公告)号：US20050224797A1

公开(公告)日：2005-10-13

申请号：US10816562

申请日：2004-04-01

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04

CPC classification number: H01L29/045 ,  H01L21/76264 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

Abstract: A microelectronic device including a first substrate bonded to a second substrate. The first and second substrate may have different crystallographic orientations. The first substrate includes an opening through which an epitaxially grown portion of the second substrate extends. A first semiconductor device is coupled to the first substrate. A second semiconductor device is coupled to the epitaxially grown portion of the second substrate.

Abstract translation: 一种微电子器件，包括接合到第二衬底的第一衬底。 第一和第二基底可以具有不同的晶体取向。 第一衬底包括第二衬底的外延生长部分延伸通过的开口。 第一半导体器件耦合到第一衬底。 第二半导体器件耦合到第二衬底的外延生长部分。

公开(公告)号：US06949443B2

公开(公告)日：2005-09-27

申请号：US10683901

申请日：2003-10-10

Applicant: Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

Inventor： Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78 ,  H01L29/80

CPC classification number: H01L29/7846 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7842

Abstract: A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.

Abstract translation: 公开了一种改进的驱动电流的高性能半导体器件及其制造方法。 半导体器件具有构建在有源区上的源极和漏极区域，器件的长度与其宽度不同。 在有源区周围制造一个或多个隔离区域，然后用退火处理后其体积收缩率超过0.5％的预定隔离材料填充隔离区域。 在有源区上形成栅电极，并且在栅电极旁边形成一个或多个电介质间隔物。 然后，接触蚀刻停止层放置在器件上，其中隔离区，间隔物和接触蚀刻层有助于调制施加在有源区上的净应变，以便改善驱动电流。

公开(公告)号：US20050170594A1

公开(公告)日：2005-08-04

申请号：US11093847

申请日：2005-03-30

Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/165 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

Abstract: A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

Abstract translation: 具有晶格失配区的应变通道晶体管结构及其制造方法。 晶体管结构包括具有应变沟道区的衬底，包括表面上具有第一自然晶格常数的第一半导体材料，覆盖在应变沟道区上的栅极电介质层，覆盖栅极电介质层的栅电极和源极 区域和漏极区域相邻地邻近应变通道区域，其中源区域和漏极区域中的一个或两个包括晶格失配区域，该区域和漏极区域包括具有不同于第一自然晶格常数的第二自然晶格常数的第二半导体材料。