公开(公告)号：US08088637B1

公开(公告)日：2012-01-03

申请号：US12435333

申请日：2009-05-04

申请人： William S. Wong ,  Michael A. Kneissl ,  Zhihong Yang ,  Mark Teepe ,  Cliff Knollenberg

发明人： William S. Wong ,  Michael A. Kneissl ,  Zhihong Yang ,  Mark Teepe ,  Cliff Knollenberg

IPC分类号： H01L21/00

CPC分类号： H01L29/205 ,  B82Y20/00 ,  H01L29/155 ,  H01L29/2003 ,  H01L33/04 ,  H01L33/32 ,  H01S5/0213 ,  H01S5/0216 ,  H01S5/0217 ,  H01S5/0224 ,  H01S5/34333

摘要： A GaN/AlN superlattice is formed over a GaN/sapphire template structure, serving in part as a strain relief layer for growth of subsequent layers (e.g., deep UV light emitting diodes). The GaN/AlN superlattice mitigates the strain between a GaN/sapphire template and a multiple quantum well heterostructure active region, allowing the use of high Al mole fraction in the active region, and therefore emission in the deep UV wavelengths.

摘要翻译： 在GaN /蓝宝石模板结构上形成GaN / AlN超晶格，其部分作为用于后续层（例如深UV发光二极管）生长的应变消除层。 GaN / AlN超晶格减轻GaN /蓝宝石模板和多量子阱异质结构有源区之间的应变，允许在有源区中使用高Al摩尔分数，从而在深紫外波长中发射。

公开(公告)号：US08040729B2

公开(公告)日：2011-10-18

申请号：US12621801

申请日：2009-11-19

申请人： William S. Wong ,  Sanjiv Sambandan ,  Tse Nga Ng ,  Robert A. Street

发明人： William S. Wong ,  Sanjiv Sambandan ,  Tse Nga Ng ,  Robert A. Street

IPC分类号： G11C16/04

CPC分类号： G11C13/003 ,  B82Y10/00 ,  G11C11/22 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/53 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/80

摘要： A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic.A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

摘要翻译： 包括数据线的存储单元阵列; 电容器 以及耦合在数据线和电容器之间的晶体管。 电容器和晶体管中的至少一个包括具有可变电特性的材料。 存储单元阵列，包括耦合在第一节点，第二节点和第三节点之间的第一晶体管; 以及耦合在所述第二节点和第四节点之间的第二晶体管。 第一晶体管包括具有可变电特征的材料。

公开(公告)号：US07749396B2

公开(公告)日：2010-07-06

申请号：US11388731

申请日：2006-03-24

申请人： Eugene M. Chow ,  William S. Wong ,  Michael Chabinyc ,  Ana Claudia Arias

发明人： Eugene M. Chow ,  William S. Wong ,  Michael Chabinyc ,  Ana Claudia Arias

IPC分类号： H01B13/00 ,  C23F1/00

CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L27/1292

摘要： A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.

摘要翻译： 一种在晶体管上制造诸如小栅电极的精细特征的工艺。 该方法涉及一种掩模的喷墨印刷和金属镀层，以在一层中制造亚像素和标准像素尺寸特征。 打印创建一个小的子像素大小的间隙掩模，用于电镀精细特征。 可以使用第二印刷掩模来保护新形成的栅极并蚀刻连接小栅极的标准像素尺寸线。

公开(公告)号：US20100148188A1

公开(公告)日：2010-06-17

申请号：US12337561

申请日：2008-12-17

申请人： Clifford F. Knollenberg ,  William S. Wong ,  Christopher L. Chua

发明人： Clifford F. Knollenberg ,  William S. Wong ,  Christopher L. Chua

IPC分类号： H01L33/00 ,  H01L21/78 ,  H01L29/66

CPC分类号： H01L21/268 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/66462 ,  H01L33/0075 ,  H01L33/0095

摘要： An embodiment is a method and apparatus to induce flaw formation in nitride semiconductors. Regions of a thin film structure are selectively decomposed within a thin film layer at an interface with a substrate to form flaws in a pre-determined pattern within the thin film structure. The flaws locally concentrate stress in the pre-determined pattern during a stress-inducing operation. The stress-inducing operation is performed. The stress-inducing operation causes the thin film layer to fracture at the pre-determined pattern.

摘要翻译： 一个实施方案是在氮化物半导体中诱导缺陷形成的方法和装置。 薄膜结构的区域在与基板的界面处的薄膜层内选择性地分解，以在薄膜结构内以预定图案形成缺陷。 在应力诱导操作期间，缺陷将应力局部集中在预定模式中。 执行应力诱导操作。 应力诱导操作导致薄膜层以预定图案断裂。

公开(公告)号：US20100096729A1

公开(公告)日：2010-04-22

申请号：US12253390

申请日：2008-10-17

申请人： William S. Wong ,  Brent S. Krusor ,  Robert A. Street

发明人： William S. Wong ,  Brent S. Krusor ,  Robert A. Street

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H05K3/0044 ,  G02F2201/56 ,  H01L27/14603 ,  H01L27/14692 ,  H01L27/14812 ,  H01L29/78603

摘要： A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure. A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being arranged to as to increase a radius of curvature to meet a stress relief parameter when the substrate is shaped, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure. A three-dimensional electronic device having an electronic device formed on a flexible substrate, the flexible substrate formed into a three-dimensional structure, wedged-shaped portions removed from the substrate to allow the substrate to be formed into the three-dimensional structure, and a stress relief feature arranged adjacent to the wedge-shaped portions.

摘要翻译： 形成三维电子器件的方法包括在二维柔性基板上形成至少一个电子器件，该电子器件根据三维结构形成，切割二维柔性基片，切割 定位成允许二维基底成形，切口具有至少一个应力消除特征，并且成形二维柔性基底以形成三维结构，应力消除特征被设置为减轻二维基底中的应力 三维结构。 形成三维电子器件的方法包括在二维柔性基板上形成至少一个电子器件，该电子器件根据三维结构形成，切割二维柔性基片，切割 被布置成当基底成形时增加曲率半径以满足应力消除参数，并且将二维柔性基底成形以形成三维结构。 一种具有形成在柔性基板上的电子器件的三维电子器件，形成为三维结构的柔性衬底，从衬底移除楔形部分以使衬底形成三维结构;以及 紧邻楔形部分布置的应力消除特征。

公开(公告)号：US20100068856A1

公开(公告)日：2010-03-18

申请号：US12622210

申请日：2009-11-19

申请人： William S. Wong ,  Sanjiv Sambandan ,  Tse Nga Ng ,  Robert A. Street

发明人： William S. Wong ,  Sanjiv Sambandan ,  Tse Nga Ng ,  Robert A. Street

IPC分类号： H01L21/8242 ,  H01L21/82

CPC分类号： G11C13/003 ,  B82Y10/00 ,  G11C11/22 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/53 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/80

摘要： A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic.A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

公开(公告)号：US07679951B2

公开(公告)日：2010-03-16

申请号：US11962976

申请日：2007-12-21

申请人： William S. Wong ,  Sanjiv Sambandan ,  Tse Nga Ng ,  Robert A. Street

发明人： William S. Wong ,  Sanjiv Sambandan ,  Tse Nga Ng ,  Robert A. Street

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  B82Y10/00 ,  G11C11/22 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/53 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/80

摘要： A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic.A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

摘要翻译： 包括数据线的存储单元阵列; 电容器 以及耦合在数据线和电容器之间的晶体管。 电容器和晶体管中的至少一个包括具有可变电特性的材料。 存储单元阵列，包括耦合在第一节点，第二节点和第三节点之间的第一晶体管; 以及耦合在所述第二节点和第四节点之间的第二晶体管。 第一晶体管包括具有可变电特性的材料。

公开(公告)号：US20090053845A1

公开(公告)日：2009-02-26

申请号：US12265379

申请日：2008-11-05

申请人： William S. Wong ,  Michael A. Kneissl ,  Mark Teepe

发明人： William S. Wong ,  Michael A. Kneissl ,  Mark Teepe

IPC分类号： H01L21/18

CPC分类号： H01L33/0079 ,  B82Y20/00 ,  H01L21/30621 ,  H01S5/0213 ,  H01S5/0216 ,  H01S5/0217 ,  H01S5/32341 ,  H01S5/34333

摘要： A system and method for providing improved surface quality following removal of a substrate and template layers from a semiconductor structure provides an improved surface quality for a layer (such as a quantum well heterostructure active region) prior to bonding a heat sink/conductive substrate to the structure. Following the physical removal of a sapphire substrate, a sacrificial coating such as a spin-coat polymer photoresist is applied to an exposed GaN surface. This sacrificial coating provides a planar surface, generally parallel to the planes of the interfaces of the underlying layers. The sacrificial coating and etching conditions are selected such that the etch rate of the sacrificial coating approximately matches the etch rate of GaN and the underlying layers, so that the physical surface profile during etching approximates the physical surface profile of the sacrificial coating prior to etching. Following etching, a substrate is bonded to the exposed surface which acts as a heat sink and may be conductive providing for backside electrical contact to the active region.

摘要翻译： 在从半导体结构去除衬底和模板层之后提供改进的表面质量的系统和方法在将散热器/导电衬底接合到衬底之前为层（例如量子阱异质结构有源区）提供改进的表面质量 结构体。 在物理去除蓝宝石衬底之后，将诸如旋涂聚合物光致抗蚀剂的牺牲涂层施加到暴露的GaN表面。 该牺牲涂层提供了一般平行于下层的界面的平面的平面。 选择牺牲涂层和蚀刻条件使得牺牲涂层的蚀刻速率近似与GaN和下面的层的蚀刻速率匹配，使得蚀刻期间的物理表面轮廓近似于蚀刻之前牺牲涂层的物理表面轮廓。 在蚀刻之后，衬底被结合到作为散热器的暴露表面，并且可以是导电的，用于与有源区域的背面电接触。

公开(公告)号：US07344928B2

公开(公告)日：2008-03-18

申请号：US11193847

申请日：2005-07-28

申请人： William S. Wong ,  Rene A. Lujan ,  Eugene M. Chow

发明人： William S. Wong ,  Rene A. Lujan ,  Eugene M. Chow

IPC分类号： H01L21/84

CPC分类号： H01L29/41733 ,  H01L27/124 ,  H01L27/1285 ,  H01L27/1288 ,  H01L27/1292 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757

摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.

摘要翻译： 公开了一种自对准薄膜顶栅晶体管及其制造方法。 通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。 然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。 在其上形成半导体层和绝缘层。 然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。 在感光材料的显影之后，沉积栅极金属层。 然后再次通过数字光刻法在器件上形成第二印刷图案掩模。 蚀刻和去除感光材料离开自对准顶栅电极。

公开(公告)号：US07234214B2

公开(公告)日：2007-06-26

申请号：US11084579

申请日：2005-03-18

申请人： Baomin Xu ,  Steven A. Buhler ,  Michael C. Weisberg ,  William S. Wong ,  Scott E. Solberg ,  Karl A. Littau ,  John S. Fitch ,  Scott A. Elrod

发明人： Baomin Xu ,  Steven A. Buhler ,  Michael C. Weisberg ,  William S. Wong ,  Scott E. Solberg ,  Karl A. Littau ,  John S. Fitch ,  Scott A. Elrod

IPC分类号： H04R17/00

CPC分类号： B41J2/161 ,  B41J2/1623 ,  B41J2/1632 ,  B41J2/1634 ,  B41J2/1637 ,  B41J2/1646 ,  H01L41/313 ,  H01L41/314 ,  H01L41/331 ,  H01L2221/68368 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49155 ,  Y10T29/4981

摘要： A method of producing at least one thick film element, including depositing a material on a surface of at least one first substrate to form at least one thick film element structure having a thickness of approximately greater than 10 μm to 100 μm. Then, then the at least one thick film element structure is bonded to a second substrate, and the at least one first substrate is removed from the at least one thick film element structure using a lift-off process employing radiation energy. The lift-off process including emitting, from a radiation source, a radiation beam through the first substrate to an attachment interface formed between the first substrate and the at least one thick film element structure at the first surface of the first substrate. The first substrate being substantially transparent at the wavelength of the radiation beam, permitting the radiation beam to generate sufficient energy at the interface to break the attachment.

摘要翻译： 一种生产至少一个厚膜元件的方法，包括在至少一个第一基底的表面上沉积材料以形成至少一个厚度大约在10至100μm的厚膜元件结构。 然后，将至少一个厚膜元件结构接合到第二基板，并且使用采用辐射能的剥离工艺将至少一个第一基板从至少一个厚膜元件结构移除。 剥离过程包括从辐射源将辐射束从第一衬底发射到在第一衬底的第一表面处形成在第一衬底和至少一个厚膜元件结构之间的附接界面。 第一衬底在辐射束的波长处基本上是透明的，允许辐射束在界面处产生足够的能量以破坏附件。