公开(公告)号：US20060107267A1

公开(公告)日：2006-05-18

申请号：US11270515

申请日：2005-11-10

申请人： Ryoko Miyachi ,  Hajime Ogawa ,  Tomoo Hamada ,  Teruo Kawabata

发明人： Ryoko Miyachi ,  Hajime Ogawa ,  Tomoo Hamada ,  Teruo Kawabata

IPC分类号： G06F9/46

CPC分类号： G06F17/505

摘要： An instruction scheduling method according to the present invention allocates each instruction included in an instruction sequence to be synthesized as a circuit to one of execution cycles in the circuit, and includes: detecting a freedom of each instruction, the freedom representing a time period within which the instruction can be allocated; calculating a load of a processing element corresponding to the instruction for each of the execution cycles; and allocating the instructions using the same processing element within the freedoms to different execution cycles based on the load.

摘要翻译： 根据本发明的指令调度方法将要合成的指令序列中包括的每个指令分配给电路中的一个执行周期，并且包括：检测每个指令的自由度，表示其中的自由度，其中 该指令可以分配; 计算与每个执行周期的指令相对应的处理元件的负载; 以及基于所述负载，在所述自由度内使用相同处理元件将指令分配给不同的执行周期。

公开(公告)号：US06976245B2

公开(公告)日：2005-12-13

申请号：US10012725

申请日：2001-10-22

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G09F9/44

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当分支指令由指令解码器409a〜409c解码时，分支指令中包含的PC相对值的高29位被发送到上PC计算器411，低3位被发送到下PC计算器 405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US20050144420A1

公开(公告)日：2005-06-30

申请号：US10995148

申请日：2004-11-24

申请人： Shohei Michimoto ,  Hajime Ogawa ,  Taketo Heishi ,  Kiyoshi Nakashima ,  Hazuki Okabayashi ,  Ryuta Nakanishi

发明人： Shohei Michimoto ,  Hajime Ogawa ,  Taketo Heishi ,  Kiyoshi Nakashima ,  Hazuki Okabayashi ,  Ryuta Nakanishi

IPC分类号： G06F9/30 ,  G06F9/355 ,  G06F9/38 ,  G06F9/45 ,  G06F12/08

CPC分类号： G06F9/342 ,  G06F8/4442 ,  G06F9/383 ,  G06F12/0862 ,  G06F12/0888 ,  G06F2212/6028

摘要： The data processing apparatus capable of efficiently using a cache memory includes: a cache memory 28 and a memory 30 that stores an instruction or data in each area specified by a physical address; an arithmetic processing unit 22 that outputs a logical address including the physical address and process determining data indicating a prescribed process, obtains the instruction or the data corresponding to the physical address included in the logical address, and execute the instruction; an address conversion unit 26 that converts the logical address outputted by the arithmetic processing unit 22 into the physical address. The data processing apparatus reads the instruction or the data stored in areas specified by the physical address, in the cache memory 28 and the memory 30, and executes a prescribed process based on the process determining data.

摘要翻译： 能够有效地使用高速缓冲存储器的数据处理装置包括：高速缓存存储器28和存储由物理地址指定的每个区域中的指令或数据的存储器30; 输出包括表示规定处理的物理地址和处理确定数据的逻辑地址的算术处理单元22，获得与包含在逻辑地址中的物理地址相对应的指令或数据，并执行指令; 地址转换单元26，其将由运算处理单元22输出的逻辑地址转换成物理地址。 数据处理装置读取存储在高速缓冲存储器28和存储器30中由物理地址指定的区域中的指令或数据，并根据处理确定数据执行规定的处理。

公开(公告)号：US5801352A

公开(公告)日：1998-09-01

申请号：US525024

申请日：1995-09-08

申请人： Atsushi Taneda ,  Koji Akamatsu ,  Hajime Ogawa ,  Satoshi Suzuki

发明人： Atsushi Taneda ,  Koji Akamatsu ,  Hajime Ogawa ,  Satoshi Suzuki

IPC分类号： B23H1/02 ,  B23H7/14

CPC分类号： B23H1/022

摘要： A power supply unit for a discharge machining apparatus which eliminates overshooting in current rise and improves the electrode consumption characteristics by preventing an operational amplifier as well as a current control element from being saturated, thereby eliminating overshooting during the rise time of the machining current, by clamping the output voltage of the operational amplifier during the stand-by time for electric discharge. The output is clamped by a plurality of resistors and diodes to a state where the output voltage is higher than a power-supply voltage (the output clamp level is set by a resistor). Namely, during the stand-by time when inverted amplification (feedback) via a resistor in an operational amplifier is being carried out, a constant state of feedback is maintained by the diodes.

摘要翻译： 一种用于放电加工装置的电源单元，其通过防止运算放大器以及电流控制元件饱和来消除电流上升中的过冲并提高电极消耗特性，从而在加工电流的上升时间期间通过 在待机时间内钳位运算放大器的输出电压进行放电。 输出被多个电阻和二极管钳位到输出电压高于电源电压（输出钳位电平由电阻设置）的状态。 也就是说，在正在执行通过运算放大器中的电阻器的反相放大（反馈）的待机时间期间，二极管保持恒定的反馈状态。

公开(公告)号：US08884565B2

公开(公告)日：2014-11-11

申请号：US13467234

申请日：2012-05-09

申请人： Junichi Tezuka ,  Hajime Ogawa

发明人： Junichi Tezuka ,  Hajime Ogawa

IPC分类号： H02P27/00 ,  H02P5/74 ,  H02P27/06

CPC分类号： H02P5/74 ,  H02M2001/008 ,  H02P27/06

摘要： A motor driving device comprises: a single DC conversion unit that converts input AC into DC; a plurality of AC conversion units that convert DC output from the DC conversion unit into AC supplied to a plurality of motor units as driving electric power; an electric power consumption calculation unit of the DC conversion unit that calculates electric power consumption of the DC conversion unit from the input voltage and input current to the DC conversion unit every predetermined time period; and a maximum output calculation unit of the DC conversion unit that extracts a maximum value from the electric power consumption of the DC conversion unit calculated every predetermined time period and outputs it as a maximum output of the DC conversion unit.

摘要翻译： 电动机驱动装置包括：将输入AC转换为DC的单个DC转换单元; 多个AC转换单元，其将从DC转换单元输出的DC转换为作为驱动电力供给到多个电动机单元的AC; DC转换单元的电力消耗计算单元，其每隔预定时间段从直流转换单元的输入电压和输入电流计算出直流变换单元的电力消耗; 以及DC转换单元的最大输出计算单元，其从每个预定时间段计算的DC转换单元的电力消耗中提取最大值，并将其输出为DC转换单元的最大输出。

公开(公告)号：US20080209407A1

公开(公告)日：2008-08-28

申请号：US12109707

申请日：2008-04-25

申请人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Taketo Heishi ,  Hajime Ogawa

发明人： Hazuki Okabayashi ,  Tetsuya Tanaka ,  Taketo Heishi ,  Hajime Ogawa

IPC分类号： G06F9/45

CPC分类号： G06F9/30072 ,  G06F8/447 ,  G06F9/325

摘要： The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction “jloop C6,C1:C4,TAR,Ra”, the processor (i) sets a conditional flag C4 to 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag C2 to a conditional flag C1, moves the value of a conditional flag C3 to the conditional flag C2, and moves the value of the conditional flag C4 to the conditional flags C3 and C6, (iii) adds −1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.

摘要翻译： 本发明提供了一种具有小规模电路并且能够在消耗少量功率的同时高速执行循环处理的处理器。 当处理器解码指​​令“jloop C 6，C 1：C 4，TAR，Ra”时，当寄存器Ra的值小于0时，处理器（i）将条件标志C 4设置为0，（ii） 将条件标志C 2的值移动到条件标志C1，将条件标志C 3的值移动到条件标志C 2，并将条件标志C 4的值移动到条件标志C 3和C 6，（iii）向寄存器Ra添加-1，并将结果存储到寄存器Ra中，（iv）分支到由分支寄存器（TAR）指定的地址。 当没有填充分支目标指令时，跳转缓冲区将用分支目标指令填充。

公开(公告)号：US20080141229A1

公开(公告)日：2008-06-12

申请号：US11969083

申请日：2008-01-03

申请人： Taketo Heishi ,  Hajime Ogawa ,  Shuichi Takayama ,  Toshiyuki Sakata ,  Shohei Michimoto

发明人： Taketo Heishi ,  Hajime Ogawa ,  Shuichi Takayama ,  Toshiyuki Sakata ,  Shohei Michimoto

IPC分类号： G06F9/45 ,  G06F9/312

CPC分类号： G06F9/30094 ,  G06F9/30021 ,  G06F9/30072

摘要： The first, second, and third operating units 441 to 443 each perform a predetermined operation according to an instruction before a point of time partway through a clock cycle. When having performed a comparison operation, each operating unit outputs a result value to the condition flag operating unit 51. The condition flag operating unit 51 calculates a new condition flag value by performing a logical operation on either (a) a value that has been read from the condition flag register 46 and the result value or (b) the result values themselves. The condition flag operating unit 51 outputs, before the clock cycle ends, the new condition flag value to one of the first, second, and third gates 451 to 453 that is related to a conditional instruction so as to control nullification of the conditional new condition flag value.

摘要翻译： 第一，第二和第三操作单元441至443各自根据在时钟周期的中途的时间点之前的指令执行预定的操作。 当执行比较操作时，每个操作单元将结果值输出到条件标志操作单元51。 条件标志操作单元51通过对（a）从条件标志寄存器46读取的值和结果值或（b）结果值本身执行逻辑运算来计算新条件标志值。 条件标志操作单元51在时钟周期结束之前将新条件标志值输出到与条件指令相关的第一，第二和第三门451至453中的一个，以便控制条件新条件的无效 标志值。

公开(公告)号：US20080046687A1

公开(公告)日：2008-02-21

申请号：US11896368

申请日：2007-08-31

申请人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

发明人： Tetsuya Tanaka ,  Hazuki Okabayashi ,  Taketo Heishi ,  Hajime Ogawa ,  Tsuneyuki Suzuki ,  Tokuzo Kiyohara ,  Takeshi Tanaka ,  Hideshi Nishida ,  Masaki Maeda

IPC分类号： G06F9/302 ,  G06F15/80

CPC分类号： G06F9/30025 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167

摘要： A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.

公开(公告)号：US07284241B2

公开(公告)日：2007-10-16

申请号：US10630705

申请日：2003-07-31

申请人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

发明人： Taketo Heishi ,  Toshiyuki Sakata ,  Hajime Ogawa ,  Ryoko Miyachi ,  Shuji Miyasaka ,  Tomokazu Ishikawa

IPC分类号： G06F9/45

CPC分类号： G06F8/443 ,  G06F8/425 ,  G06F8/427 ,  G06F8/4441

摘要： An operator definition file 102 and the like included in a source program 101 and a compiler 100 that translates the source program 101 into a machine language program 105 are provided. The operator definition file 102 includes definitions of various fixed point type operators by class definitions. The compiler 100 can generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compiler 100 is made up of an intermediate code generation unit 121 that generates intermediate codes, a machine language instruction substitution unit 122 that substitutes the intermediate codes referring to classes defined by the operator definition file 102 with machine language instructions and an optimization unit 130 that performs optimization targeting the intermediate codes including the substituted machine language instructions.

摘要翻译： 提供包括在源程序101中的操作者定义文件102等以及将源程序101转换为机器语言程序105的编译器100。 操作者定义文件102包括通过类定义的各种定点类型操作符的定义。 编译器100可以生成有效的高级特定指令，处理器执行并通过扩展功能等进行改进，而不会重复频繁升级编译器本身的版本。 编译器100由生成中间代码的中间代码生成单元121构成，机器语言指令替换单元122，其使用机器语言指令代替参考由操作者定义文件102定义的类别的中间代码和优化单元130， 执行针对包括替代机器语言指令的中间代码的优化。

公开(公告)号：US07076638B2

公开(公告)日：2006-07-11

申请号：US10246482

申请日：2002-09-19

申请人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

发明人： Taketo Heishi ,  Shuichi Takayama ,  Tetsuya Tanaka ,  Hajime Ogawa ,  Nobuo Higaki

IPC分类号： G06F9/30

CPC分类号： G06F9/3853 ,  G06F9/30072 ,  G06F9/3822

摘要： In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.