利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

94 条记录 (耗时 0.04 秒)

    Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance and method of manufacturing same
    51.
    发明授权
    Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance and method of manufacturing same 有权
    包括具有增加的信息存储电容的存储单元的存储器件的半导体集成电路器件及其制造方法

    公开(公告)号：US6023084A

    公开(公告)日：2000-02-08

    申请号：US174332

    申请日：1998-10-19

    申请人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

    发明人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

    IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/10 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L2924/0002

    摘要： A semiconductor memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, and the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.

    摘要翻译： 半导体存储器件具有半导体衬底和设置在字线导体和位线导体之间的交叉点处的存储单元。 每个位线导体的相邻的两个存储单元形成存储单元对单元结构，其中相邻两个存储单元的晶体管的第一半导体区域在其边界处被结合成单个区域并连接到位线导体之一 通过位线连接导体，相邻的两个存储单元的晶体管的栅电极分别连接到彼此相邻的字线导体，并且相邻两个存储单元的晶体管的第二半导体区域连接到 各信息存储电容器。 形成在一个位线导体下方的一系列存储单元对单元结构相对于分别在一个位线导体的相对侧上相邻的相邻第一和第二位线导体下形成的一系列存储单元对单元结构位置移位，使得 形成在相邻的第一位线导体下方的存储单元对单元结构的第二信息存储电容器和形成在相邻的第二位线导体下方的存储单元对单元结构的第一信息存储电容器位于邻近位线连接导体 形成在一个位线导体下的存储单元对单元结构。

    Controller for absorption cold or hot water generating machine
    52.
    发明授权
    Controller for absorption cold or hot water generating machine 失效
    控制器用于吸收冷热水机

    公开(公告)号：US6009714A

    公开(公告)日：2000-01-04

    申请号：US116943

    申请日：1998-07-17

    申请人： Syouji Tanaka ,  Takashi Kaneko ,  Naoyuki Inoue ,  Jun Murata ,  Teruwo Shiraishi ,  Toshio Matsubara ,  Nobutaka Matsuda ,  Motonao Kera

    发明人： Syouji Tanaka ,  Takashi Kaneko ,  Naoyuki Inoue ,  Jun Murata ,  Teruwo Shiraishi ,  Toshio Matsubara ,  Nobutaka Matsuda ,  Motonao Kera

    IPC分类号： F25B15/00 ,  F25B49/04

    CPC分类号： F25B49/043 ,  F25B15/008 ,  Y02B30/62

    摘要： A controller for an absorption cold/hot water generating machine, in which a refrigerating cycle is formed by pipe-connecting an evaporator, an absorber, a solution heat exchanger, a low-temperature generator, a condenser, and a high-temperature generator, and the solution level in a header of the high-temperature generator is kept within a prescribed range by controlling the flow rate of the solution fed from the absorber to the high-temperature generator; wherein a solution pump for feeding a solution from the absorber to the high-temperature generator is inverter-driven, and there is provided pressure difference detecting means for detecting a difference in pressure between the high-temperature generator and the absorber; and wherein there is provided control means which controls the solution pump driving frequency of the inverter as a function of a pressure difference between the high-temperature generator and the absorber.

    摘要翻译： 一种用于吸收冷热水机的控制器，其中通过蒸发器，吸收器，溶液热交换器，低温发生器，冷凝器和高温发生器的管连接形成冷冻循环， 并且通过控制从吸收器供给到高温发生器的溶液的流量，将高温发生器的集管中的溶液水平保持在规定范围内; 其特征在于，将来自所述吸收体的溶液供给到所述高温发生器的溶液泵由逆变器驱动，并且设置有用于检测所述高温发生器与所述吸收器之间的压力差的压力差检测单元; 并且其中设置有控制装置，其控制逆变器的溶液泵驱动频率作为高温发生器和吸收器之间的压力差的函数。

    Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance and method of manufacturing same
    54.
    发明授权
    Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance and method of manufacturing same 失效
    包括具有增加的信息存储电容的存储单元的存储器件的半导体集成电路器件及其制造方法

    公开(公告)号：US5831300A

    公开(公告)日：1998-11-03

    申请号：US731489

    申请日：1996-10-16

    申请人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

    发明人： Yoshitaka Tadaki ,  Jun Murata ,  Toshihiro Sekiguchi ,  Hideo Aoki ,  Keizo Kawakita ,  Hiroyuki Uchiyama ,  Michio Nishimura ,  Michio Tanaka ,  Yuji Ezaki ,  Kazuhiko Saitoh ,  Katsuo Yuhara ,  Songsu Cho

    IPC分类号： H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/10 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L2924/0002

    摘要： A semiconductor memory device has a semiconductor substrate, word line conductors and bit line conductors, and memory cells provided at intersections between the word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to the series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.

    摘要翻译： 半导体存储器件具有半导体衬底，字线导体和位线导体以及设置在字线导体和位线导体之间的交叉点处的存储单元。 每个位线导体的相邻的两个存储单元形成存储单元对单元结构，其中相邻两个存储单元的晶体管的第一半导体区域在其边界处被结合成单个区域并连接到位线导体之一 通过位线连接导体，相邻的两个存储单元的晶体管的栅电极分别连接到彼此相邻的字线导体，相邻两个存储单元的晶体管的第二半导体区域连接到相应的两个存储单元的晶体管的第二半导体区域 信息存储电容器。 形成在一个位线导体下方的一系列存储单元对单元结构相对于分别形成在一个位线导体的相对侧上相邻的第一和第二位线导体之下的一系列存储单元对单元结构位移地移位， 形成在相邻的第一位线导体下方的存储单元对单元结构的第二信息存储电容器和形成在相邻的第二位线导体下方的存储单元对单元结构的第一信息存储电容器位于与位线连接 形成在一个位线导体下的存储单元对单元结构的导体。

    Charging member containing reduced titanium oxide and device using same
    60.
    发明授权
    Charging member containing reduced titanium oxide and device using same 失效
    含有还原氧化钛的充电构件和使用其的装置

    公开(公告)号：US5270768A

    公开(公告)日：1993-12-14

    申请号：US871547

    申请日：1992-04-21

    申请人： Jun Murata

    发明人： Jun Murata

    IPC分类号： G03G15/02 ,  G03G15/16 ,  G03G21/00

    CPC分类号： G03G15/1685 ,  G03G15/0233

    摘要： A charging member for use in a device, such as an electrophotographic or facsimile device, includes at least inner and outer resistance layers formed on an electrically-conductive substrate. Electrically-conductive particles dispersed in the matrix of the outer resistance layer are reduced titanium oxide which is represented by the following general formula:TiOnwhere n is a number not more than 1.9.