公开(公告)号：US20070210364A1

公开(公告)日：2007-09-13

申请号：US11547904

申请日：2005-04-21

申请人： Kiyoshi Kato ,  Yutaka Shionoiri

发明人： Kiyoshi Kato ,  Yutaka Shionoiri

IPC分类号： H01L27/108

CPC分类号： H01L27/1266 ,  G02F1/136213 ,  H01L21/288 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76838 ,  H01L27/0811 ,  H01L27/10805 ,  H01L27/1214 ,  H01L27/13 ,  H01L29/04 ,  H01L29/78675

摘要： A capacitor capable of functioning as a capacitor even when an AC voltage is applied thereto is provided without increasing the manufacturing steps of a semiconductor device. A transistor is used as a MOS capacitor where a pair of impurity regions formed on opposite sides of a channel formation region are each doped with impurities of different conductivity so as to be used as a source region or a drain region. Specifically, assuming that an impurity region that is doped with N-type impurities is referred to as an N-type region while an impurity region that is doped with P-type impurities is referred to as a P-type region, a transistor is provided where a channel formation region is interposed between the N-type region and the P-type region, which is used as a MOS capacitor.

摘要翻译： 在不增加半导体器件的制造步骤的情况下，即使在施加交流电压的情况下，也可以提供能够作为电容器起作用的电容器。 晶体管用作MOS电容器，其中形成在沟道形成区域的相对侧上的一对杂质区域各自掺杂有不同导电性的杂质，以便用作源极区域或漏极区域。 具体地说，假定掺杂有N型杂质的杂质区域称为N型区域，而掺杂有P型杂质的杂质区域称为P型区域，则提供晶体管 其中沟道形成区域被插入在用作MOS电容器的N型区域和P型区域之间。

公开(公告)号：US07166863B2

公开(公告)日：2007-01-23

申请号：US10941823

申请日：2004-09-16

申请人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Atsuo Isobe ,  Hidekazu Miyairi ,  Hideomi Suzawa ,  Yutaka Shionoiri ,  Hiroyuki Miyake

发明人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Atsuo Isobe ,  Hidekazu Miyairi ,  Hideomi Suzawa ,  Yutaka Shionoiri ,  Hiroyuki Miyake

IPC分类号： H01L29/04 ,  H01L31/036

CPC分类号： H01L21/02609 ,  H01L21/2026 ,  H01L27/12 ,  H01L27/1281 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78675 ,  H01L29/78696

摘要： A semiconductor element which is capable of operating at a high speed, high in an electric current drive capability, and small in fluctuation among a plurality of elements, and a semiconductor device including the semiconductor element are provided. The semiconductor element has a first crystalline semiconductor region including plural crystal orientations without practically having a grain boundary on an insulating surface, the first crystalline semiconductor region being provided to be jointly connected to a conductive region including the first crystalline semiconductor region and a second crystalline semiconductor region, in which the conductive region is provided astride insulating films extending in a linear stripe pattern.

摘要翻译： 提供能够高速运行，电流驱动能力高，多个元件之间波动小的半导体元件，以及包括半导体元件的半导体器件。 半导体元件具有包括多个晶体取向的第一晶体半导体区域，而绝缘表面实际上不具有晶界，第一晶体半导体区域被设置为共同连接到包括第一晶体半导体区域的导电区域和第二晶体半导体区域 区域，其中导电区域被设​​置成跨过线性条纹图案延伸的绝缘膜。

公开(公告)号：US20050007156A1

公开(公告)日：2005-01-13

申请号：US10899048

申请日：2004-07-27

申请人： Yutaka Shionoiri ,  Kiyoshi Kato ,  Munehiro Azami

发明人： Yutaka Shionoiri ,  Kiyoshi Kato ,  Munehiro Azami

IPC分类号： G11C7/06 ,  G11C11/413 ,  H03K5/22

CPC分类号： H03F3/45179 ,  G01R19/00 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/413 ,  G11C2207/063 ,  H03F3/45183 ,  H03F3/45188 ,  H03F2203/45396 ,  H03F2203/45506 ,  H03F2203/45546 ,  H03F2203/45551 ,  H03F2203/45702 ,  H03F2203/45726

摘要： A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

摘要翻译： 根据本发明的用于检测输入到第一输入端和第二输入端的信号的电位差的读出放大器包括：第一装置，用于将对应于第一和第二晶体管的阈值电压的电压施加到栅极源电压 第一和第二晶体管，以及用于将输入到第一和第二输入端的信号传送到第一和第二晶体管的栅极的第二装置。 在这种情况下，校正第一和第二晶体管的阈值变化。

公开(公告)号：US08809851B2

公开(公告)日：2014-08-19

申请号：US13101644

申请日：2011-05-05

申请人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Yusuke Sekine ,  Kazuma Furutani ,  Hiromichi Godo

发明人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Yusuke Sekine ,  Kazuma Furutani ,  Hiromichi Godo

IPC分类号： H01L29/12

CPC分类号： H01L29/7869 ,  G11C16/0433 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/40 ,  H01L29/41733 ,  H01L29/78621

摘要： A semiconductor device including a first transistor and a second transistor and a capacitor which are over the first transistor is provided. A semiconductor layer of the second transistor includes an offset region. In the second transistor provided with an offset region, the off-state current of the second transistor can be reduced. Thus, a semiconductor device which can hold data for a long time can be provided.

摘要翻译： 提供了包括在第一晶体管之上的第一晶体管和第二晶体管和电容器的半导体器件。 第二晶体管的半导体层包括偏移区域。 在设置有偏移区域的第二晶体管中，可以减小第二晶体管的截止电流。 因此，可以提供能够长时间保持数据的半导体器件。

公开(公告)号：US08716814B2

公开(公告)日：2014-05-06

申请号：US11571859

申请日：2005-07-07

申请人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Jun Koyama ,  Yutaka Shionoiri

发明人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Jun Koyama ,  Yutaka Shionoiri

IPC分类号： H01L27/14

CPC分类号： H01L27/1222 ,  G06K19/0723 ,  H01L23/5387 ,  H01L23/66 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/13 ,  H01L29/78621 ,  H01L29/78648 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.

摘要翻译： 本发明提供一种处理器，其通过在对热敏感的基板（例如塑料基板或塑料膜基板）上形成使用多晶半导体的高功能集成电路。 此外，本发明提供一种无线发送和接收电力或信号的无线处理器，无线存储器及其信息处理系统。 根据本发明，一种信息处理系统包括一个元件形成区域，该元件形成区域包括晶体管，该晶体管至少具有由半导体膜形成的沟道形成区域，半导体膜分隔成10至200nm的厚度的岛状物以及天线。 晶体管固定在柔性基板上。 其中形成包括元件形成区域的高功能集成电路并且半导体器件通过天线发送和接收数据的无线处理器。

公开(公告)号：US20120293201A1

公开(公告)日：2012-11-22

申请号：US13469143

申请日：2012-05-11

申请人： Masashi Fujita ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Hidetomo Kobayashi

发明人： Masashi Fujita ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Hidetomo Kobayashi

IPC分类号： H03K19/173

CPC分类号： H03K19/17728 ,  H03K19/1737 ,  H03K19/17772 ,  H03K19/17776

摘要： An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

摘要翻译： 目的是提供即使在电源电压停止之后也能够维持逻辑电路单元之间的连接关系或每个逻辑电路单元的电路配置的半导体器件。 另一个目的是提供一种半导体器件，其中可以高速地改变逻辑电路单元之间的连接关系或每个逻辑电路单元的电路配置。 在可重构电路中，氧化物半导体用于存储关于电路配置，连接关系等的数据的半导体元件。 具体地，氧化物半导体用于半导体元件的沟道形成区域。

公开(公告)号：US08238476B2

公开(公告)日：2012-08-07

申请号：US13010209

申请日：2011-01-20

申请人： Kiyoshi Kato ,  Yutaka Shionoiri

发明人： Kiyoshi Kato ,  Yutaka Shionoiri

IPC分类号： H03K9/00

CPC分类号： G06K19/07749 ,  H01L27/1214 ,  H01L27/1266 ,  H01L27/13

摘要： The invention provides a semiconductor device with high yield by reducing an effect of variations in characteristics of a semiconductor element. Further, by reducing an effect of variations in characteristics of a semiconductor element to improve productivity, an inexpensive semiconductor device can be provided. Further, an inexpensive semiconductor device can be provided by forming a semiconductor device in a large amount over a large substrate such as a glass substrate and a flexible substrate. A semiconductor device of the invention includes a demodulation signal generating circuit and an antenna or a wire for connecting the antenna. The demodulation signal generating circuit includes a demodulation circuit and a correction circuit. The correction circuit corrects a first demodulation signal generated from the demodulation circuit and generates a second demodulation signal.

摘要翻译： 本发明通过减少半导体元件的特性变化的影响来提供高产率的半导体器件。 此外，通过减少半导体元件的特性变化的影响以提高生产率，可以提供便宜的半导体器件。 此外，通过在诸如玻璃基板和柔性基板的大基板上大量地形成半导体器件，可以提供廉价的半导体器件。 本发明的半导体器件包括解调信号发生电路和用于连接天线的天线或导线。 解调信号发生电路包括解调电路和校正电路。 校正电路校正从解调电路产生的第一解调信号，并产生第二解调信号。

公开(公告)号：US08237248B2

公开(公告)日：2012-08-07

申请号：US12468284

申请日：2009-05-19

申请人： Shunpei Yamazaki ,  Yoshiaki Oikawa ,  Hironobu Shoji ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Masataka Nakada

发明人： Shunpei Yamazaki ,  Yoshiaki Oikawa ,  Hironobu Shoji ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Masataka Nakada

IPC分类号： H01L23/552

CPC分类号： G06K19/07749 ,  G06K19/07735 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1266 ,  H01L27/13 ,  H01Q1/38 ,  H01Q7/00

摘要： An object is to provide a highly reliable semiconductor device having resistance to external stress and electrostatic discharge while achieving reduction in thickness and size. Another object is to prevent defective shapes and deterioration in characteristics due to external stress or electrostatic discharge in a manufacture process to manufacture a semiconductor device with a high yield. A first insulator and a second insulator facing each other, a semiconductor integrated circuit and an antenna provided between the first insulator and the second insulator facing each other, a conductive shield provided on one surface of the first insulator, and a conductive shield provided on one surface of the second insulator are provided. The conductive shield provided on one surface of the first insulator and the conductive shield provided on one surface of the second insulator are electrically connected.

摘要翻译： 目的是提供一种具有耐外部应力和静电放电的高度可靠的半导体器件，同时实现厚度和尺寸的减小。 另一个目的是在制造过程中防止由于外部应力或静电放电而导致的形状不良和特性劣化，从而以高产率制造半导体器件。 第一绝缘体和第二绝缘体彼此面对，半导体集成电路和设置在第一绝缘体和第二绝缘体之间彼此面对的天线，设置在第一绝缘体的一个表面上的导电屏蔽和设置在第一绝缘体上的导电屏蔽 提供第二绝缘体的表面。 设置在第一绝缘体的一个表面上的导电屏蔽和设置在第二绝缘体的一个表面上的导电屏蔽电连接。

公开(公告)号：US08148818B2

公开(公告)日：2012-04-03

申请号：US12468280

申请日：2009-05-19

申请人： Shunpei Yamazaki ,  Yoshiaki Oikawa ,  Hironobu Shoji ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Masataka Nakada

发明人： Shunpei Yamazaki ,  Yoshiaki Oikawa ,  Hironobu Shoji ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Masataka Nakada

IPC分类号： H01L23/29

CPC分类号： G06K19/07749 ,  G06K19/07735 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1266 ,  H01L27/13 ,  H01Q1/2225 ,  H01Q1/2283 ,  H01Q1/526 ,  H01Q7/00

摘要： A conductive shield covering a semiconductor integrated circuit prevents electrostatic breakdown of the semiconductor integrated circuit (e.g., malfunction of a circuit and damage to a semiconductor element) due to electrostatic discharge. Further, with use of a pair of insulators between which the semiconductor integrated circuit is sandwiched, a highly reliable semiconductor having resistance can be provided while achieving reduction in the thickness and size. Moreover, also in the manufacturing process, external stress, or defective shapes or deterioration in characteristics resulted from electrostatic discharge are prevented, and thus the semiconductor device can be manufactured with high yield.

摘要翻译： 覆盖半导体集成电路的导电屏蔽防止由于静电放电而导致的半导体集成电路的静电破坏（例如，电路的故障和对半导体元件的损坏）。 此外，通过使用夹在半导体集成电路之间的一对绝缘体，可以提供具有电阻的高可靠性的半导体，同时实现厚度和尺寸的减小。 此外，在制造过程中也防止外部应力或形状不良或由静电放电导致的特性劣化，从而可以高产率制造半导体器件。

公开(公告)号：US07825447B2

公开(公告)日：2010-11-02

申请号：US11547904

申请日：2005-04-21

申请人： Kiyoshi Kato ,  Yutaka Shionoiri

发明人： Kiyoshi Kato ,  Yutaka Shionoiri

IPC分类号： H01L29/94

CPC分类号： H01L27/1266 ,  G02F1/136213 ,  H01L21/288 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76838 ,  H01L27/0811 ,  H01L27/10805 ,  H01L27/1214 ,  H01L27/13 ,  H01L29/04 ,  H01L29/78675

摘要： A capacitor capable of functioning as a capacitor even when an AC voltage is applied thereto is provided without increasing the manufacturing steps of a semiconductor device. A transistor is used as a MOS capacitor where a pair of impurity regions formed on opposite sides of a channel formation region are each doped with impurities of different conductivity so as to be used as a source region or a drain region. Specifically, assuming that an impurity region that is doped with N-type impurities is referred to as an N-type region while an impurity region that is doped with P-type impurities is referred to as a P-type region, a transistor is provided where a channel formation region is interposed between the N-type region and the P-type region, which is used as a MOS capacitor.

摘要翻译： 在不增加半导体器件的制造步骤的情况下，即使在施加有交流电压的情况下也能够作为电容器使用。 晶体管用作MOS电容器，其中形成在沟道形成区域的相对侧上的一对杂质区域各自掺杂有不同导电性的杂质，以便用作源极区域或漏极区域。 具体地说，假定掺杂有N型杂质的杂质区域称为N型区域，而掺杂有P型杂质的杂质区域称为P型区域，则提供晶体管 其中沟道形成区域被插入在用作MOS电容器的N型区域和P型区域之间。