公开(公告)号：US06246096B1

公开(公告)日：2001-06-12

申请号：US09103388

申请日：1998-06-24

申请人： Zoran Krivokapic ,  Ognjen Milic

发明人： Zoran Krivokapic ,  Ognjen Milic

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L21/26586 ,  H01L21/28079 ,  H01L29/1045 ,  H01L29/41775 ,  H01L29/66492 ,  H01L29/66583

摘要： A totally self-aligned transistor with a tungsten gate. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. A mid-gap electrode is also self-aligned to the transistor. The electrode is preferably formed from tungsten metal.

摘要翻译： 具有钨栅的全自对准晶体管。 单个掩模用于对准源极，漏极，栅极和隔离区域。 通过对这些区域使用单个掩码，覆盖误差大大降低。 中间间隙电极也与晶体管自对准。 电极优选由钨金属形成。

公开(公告)号：US06087208A

公开(公告)日：2000-07-11

申请号：US52386

申请日：1998-03-31

申请人： Zoran Krivokapic ,  Srinath Krishnan ,  Geoffrey Choh-Fei Yeap ,  Matthew Buynoski

发明人： Zoran Krivokapic ,  Srinath Krishnan ,  Geoffrey Choh-Fei Yeap ,  Matthew Buynoski

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/60

CPC分类号： H01L21/28194 ,  H01L21/26506 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/42376

摘要： A method for fabricating a MOSFET device is provided. The method includes a step of fining a gate oxide including first and second gate oxide materials. The first gate oxide material has a higher dielectric constant than the second gate oxide material. The first gate oxide material is formed to be over source/drain extension regions of the device; and the second gate oxide material is formed over a channel region of the device. The first gate oxide material has a low dielectric constant and provides for mitigating gate fringing field effects. The second gate oxide material has a high dielectric constant and provides for forming a thick gate oxide over a channel region of the device. Controlled uniform growth of the second gate oxide material is facilitated because of the thickness thereof.

摘要翻译： 提供了一种用于制造MOSFET器件的方法。 该方法包括使包含第一和第二栅极氧化物材料的栅极氧化物化的步骤。 第一栅极氧化物材料具有比第二栅极氧化物材料更高的介电常数。 第一栅极氧化物材料形成为在器件的源极/漏极延伸区域之上; 并且第二栅极氧化物材料形成在器件的沟道区域上。 第一栅极氧化物材料具有低介电常数并且用于减轻栅极边缘场效应。 第二栅极氧化物材料具有高介电常数并且提供用于在器件的沟道区域上形成厚栅极氧化物。 第二栅极氧化物材料的受控均匀生长由于其厚度而容易。

公开(公告)号：US6025235A

公开(公告)日：2000-02-15

申请号：US37488

申请日：1998-03-10

申请人： Zoran Krivokapic

发明人： Zoran Krivokapic

IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L29/423 ,  H01L21/334 ,  H01L21/335 ,  H01L21/38

CPC分类号： H01L29/41783 ,  H01L21/28114 ,  H01L21/76224 ,  H01L21/76895 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66575 ,  H01L21/2257 ,  H01L29/665 ,  H01L29/66545

摘要： A semiconductor apparatus formed on a semiconductor substrate includes a first active region in the substrate, and a second active region adjacent to the surface of the substrate separated from the first active region by a channel region. A gate oxide region may overlie at least a portion of the first and second active regions. The apparatus further includes a gate positioned over the channel region and having a first end and a second end respectively associated with the first and second active regions. The gate includes a first low conductive region and a second low conduction region at said first and second ends, respectively.A method for making the transistor structure of the present invention is also provided. In one aspect, the invention comprises: forming a transistor region on a silicon substrate, the region including a first and second spacers on a first side and a second side of the region, respectively, the spacers overlying a first oxide layer on the surface of the substrate; etching the first oxide layer leaving a first and second gaps between the first and second spacers, respectively, and the silicon substrate; forming a gate oxide layer overlying the surface of the substrate in the transistor region, the gate oxide having a thickness; and filling the transistor region with polysilicon to cover the gate oxide region.

公开(公告)号：US5879998A

公开(公告)日：1999-03-09

申请号：US890388

申请日：1997-07-09

申请人： Zoran Krivokapic

发明人： Zoran Krivokapic

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/66553 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/76895 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/665 ,  H01L29/66537

摘要： A short channel semiconductor device having source and drain regions in a substrate and a gate region on the top surface of the substrate between the source and drain regions is disclosed. In one embodiment, the method comprises: forming a device area in the silicon by forming a pattern stack, and forming pattern spacers adjacent to the pattern stack; forming a trench isolation about the pattern stack; removing the pattern spacers; depositing an epitaxial layer over the trench oxide and adjacent to the pattern stack; removing the pattern stack; and forming adaptively controlled spacers in the region to control said short channel length of the device.The apparatus of the present invention comprises: a semiconductor substrate; a source region and a drain region formed in the substrate; a gate region, comprising a first and a second oxide regions, a first control spacer and a second control spacer positioned above the substrate and adjacent to the first and second oxide regions, respectively, and a polysilicon layer positioned between the spacers; and an epitaxial layer, adjacent to the source and drain region and surrounding said first and second spacers.

摘要翻译： 公开了一种短沟道半导体器件，其在衬底中具有源极和漏极区域以及在源极和漏极区域之间的衬底顶表面上的栅极区域。 在一个实施例中，该方法包括：通过形成图案叠层在硅中形成器件区域，以及形成邻近图案层叠的图案间隔物; 围绕图案堆叠形成沟槽隔离; 去除图案间隔物; 在所述沟槽氧化物上沉积外延层并且邻近所述图案层叠; 去除图案堆栈; 以及在所述区域中形成自适应控制的间隔物以控制所述装置的所述短通道长度。 本发明的装置包括：半导体衬底; 形成在所述基板中的源极区域和漏极区域; 包括第一和第二氧化物区域的栅极区域，分别位于衬底上方并分别邻近第一和第二氧化物区域的第一控制间隔物和第二控制间隔物以及位于间隔物之间​​的多晶硅层; 以及与源极和漏极区相邻并且围绕所述第一和第二间隔物的外延层。

公开(公告)号：US5601954A

公开(公告)日：1997-02-11

申请号：US469148

申请日：1995-06-05

申请人： Zoran Krivokapic ,  Christopher A. Spence

发明人： Zoran Krivokapic ,  Christopher A. Spence

IPC分类号： G03F1/32 ,  H01L21/027 ,  G03F9/00

CPC分类号： G03F1/32

摘要： An attenuated phase shift mask comprises a first layer having a thickness to provide a transmission in the range of about 3 to 10% formed on a transparent substrate and a second layer comprising a transparent material having a thickness to provide a desired phase shift, formed on said first layer. For a phase shift of 180.degree. and i-line wavelength (365 nm), where chromium is used as the first layer, then a thickness within the range of about 25 to 75 run is employed; where silicon dioxide is used as the second layer, then a thickness of about 400 to 450 nm is employed. While the oxide may be dry-etched, an isotropic wet etch provides superior aerial images.

摘要翻译： 衰减相移掩模包括第一层，其具有提供在透明衬底上形成的大约3至10％范围内的透射率的厚度，以及包括具有提供期望相移的厚度的透明材料的第二层，形成在 说第一层。 对于使用铬作为第一层的180度和i线波长（365nm）的相移，则使用在约25至75nm范围内的厚度; 其中使用二氧化硅作为第二层，然后使用约400至450nm的厚度。 虽然氧化物可以被干蚀刻，但是各向同性的湿蚀刻提供了优异的航空图像。

公开(公告)号：US5556525A

公开(公告)日：1996-09-17

申请号：US316090

申请日：1994-09-30

申请人： Zoran Krivokapic ,  David S. Bang

发明人： Zoran Krivokapic ,  David S. Bang

IPC分类号： C23C14/34

CPC分类号： C23C14/3407

摘要： A PVD sputter system having a nonplanar target surface is disclosed. The configuration of the nonplanar target surface is adjusted to provide improved uniformity in deposition film thickness and step coverage at the peripheral boundary regions of the substrate. Emission-inducing power is distributed independently to different portions of the nonplanar target surface so as to modify the deposition profile according to substrate size and other factors.

摘要翻译： 公开了一种具有非平面靶表面的PVD溅射系统。 调整非平面目标表面的配置，以提供在衬底的周边边界区域的沉积膜厚度和台阶覆盖率的改善的均匀性。 发射诱导功率独立地分布到非平面目标表面的不同部分，以便根据衬底尺寸和其他因素改变沉积轮廓。

公开(公告)号：US20120038051A1

公开(公告)日：2012-02-16

申请号：US13281491

申请日：2011-10-26

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US07786003B1

公开(公告)日：2010-08-31

申请号：US11136569

申请日：2005-05-25

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

IPC分类号： H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US20100051897A1

公开(公告)日：2010-03-04

申请号：US12201801

申请日：2008-08-29

申请人： An Chen ,  Zoran Krivokapic

发明人： An Chen ,  Zoran Krivokapic

IPC分类号： H01L29/16 ,  H01L21/04

CPC分类号： H01L29/16 ,  B82Y10/00 ,  H01L29/1606 ,  H01L29/66234 ,  H01L29/778 ,  H01L29/78606 ,  H01L29/78684 ,  H01L51/0545 ,  H01L51/102

摘要： A graphene-based device is formed with a substrate having a trench therein, a device structure on the substrate and within the trench, a graphene layer over the device structure, and a protective layer over the graphene layer. Fabrication techniques include forming a trench in a substrate, forming a device structure within the trench, forming a graphene layer over the device structure, and forming a protective layer over the graphene layer.

摘要翻译： 基于石墨烯的器件形成有其中具有沟槽的衬底，衬底上的器件结构和沟槽内的器件结构，在器件结构上方的石墨烯层以及石墨烯层之上的保护层。 制造技术包括在衬底中形成沟槽，在沟槽内形成器件结构，在器件结构之上形成石墨烯层，并在石墨烯层上形成保护层。

公开(公告)号：US20080061359A1

公开(公告)日：2008-03-13

申请号：US11702847

申请日：2007-02-05

申请人： Chungho Lee ,  Hiroyuki Kinoshita ,  Zoran Krivokapic ,  Wei Zheng ,  Mark Chang ,  Rinji Sugino ,  Chi Chang

发明人： Chungho Lee ,  Hiroyuki Kinoshita ,  Zoran Krivokapic ,  Wei Zheng ,  Mark Chang ,  Rinji Sugino ,  Chi Chang

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a stack formed over a substrate. The stack includes a gate oxide layer and an overlying polycrystalline silicon layer. The stack further includes first and second undercut regions formed under the polycrystalline silicon layer and adjacent to the gate oxide layer. The memory cell further includes a first charge storage element formed in the first undercut region and a second charge storage element formed in the second undercut region.

摘要翻译： 本发明的实施例涉及存储单元。 存储单元包括形成在衬底上的堆叠。 堆叠包括栅极氧化物层和上覆的多晶硅层。 堆叠还包括形成在多晶硅层下方并与栅极氧化物层相邻的第一和第二底切区域。 存储单元还包括形成在第一底切区域中的第一电荷存储元件和形成在第二底切区域中的第二电荷存储元件。