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公开(公告)号：US20240007208A1
公开(公告)日：2024-01-04
申请号：US17938050
申请日：2022-10-05
发明人： Shih-Chang CHEN , Chih-Wei CHANG , Chun-Chi YU
IPC分类号： H04B17/345
CPC分类号： H04B17/345
摘要： An eye diagram measuring method includes: sampling a compensated input signal according to a reference voltage and a reference clock to obtain a first sampling result; and sampling a to-be-compensated input signal according to a scan voltage and a scan clock to obtain a second sampling result, including: (b1) storing a minimum phase and a voltage level which render the first sampling result identical to the second sampling result; (b2) increasing the voltage level and repeating operation (b1); (b3) decreasing the voltage level and repeating operation (b1); (b4) storing a maximum phase and the voltage level which render the first sampling result identical to the second sampling result; (b5) increasing the voltage level and repeating operation (b4); and (b6) decreasing the voltage level and repeating operation (b4). Voltage levels, maximum phases and minimum phases that are stored are for adjusting the reference voltage and the reference clock.
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公开(公告)号：US20230421181A1
公开(公告)日：2023-12-28
申请号：US18201997
申请日：2023-05-25
发明人： JIAN-JUN ZHOU , JIE-HONG YU
CPC分类号： H04B1/006 , H04B1/0067 , H04B1/04
摘要： An electronic device and an antenna control method are provided. The electronic device includes an antenna, a line switching circuit, a first communication chip, a second communication chip, and a logic circuit. The line switching circuit is coupled to the antenna. The first communication chip is coupled to the antenna through the line switching circuit and configured to generate a slot allocation signal. The second communication chip is coupled to the antenna through the line switching circuit and configured to generate a packet transceiving request signal. The first communication chip and the second communication chip are communication chips of different types. The logic circuit is coupled to the first communication chip and the second communication chip and configured to control the line switching circuit according to the slot allocation signal and the packet transceiving request signal.
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公开(公告)号：US20230420386A1
公开(公告)日：2023-12-28
申请号：US18322453
申请日：2023-05-23
发明人： CHIA JEN CHOU
IPC分类号： H01L23/552 , H01L23/31 , H01L23/00 , H01L21/56
CPC分类号： H01L23/552 , H01L23/3121 , H01L2224/48247 , H01L21/561 , H01L24/48
摘要： The present application discloses a semiconductor packaging structure and a manufacturing method of the same that could be commonly used for lead frame products and substrate products. The semiconductor packaging structure includes: a base layer (lead frame or organic substrate); a die, disposed on the base layer; a molding compound, filled over the base layer and surrounding the die; a shielding layer, covering the top surface and a side surface of the molding compound; and a bonding wire, having a first terminal and a second terminal, wherein the bonding wire extends the side surface of the molding compound, thus allowing the first terminal of the bonding wire to contact an inner side of the shielding layer.
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公开(公告)号：US20230419920A1
公开(公告)日：2023-12-28
申请号：US18191459
申请日：2023-03-28
发明人： CIAN-ROU WU , CHENG YUEH CHEN , CHUN-CHIEH CHAN
CPC分类号： G09G5/005 , G09G5/18 , G09G2310/08
摘要： A control device is configured to control a display panel according to a trigger signal transmitted from an input device to a host. The control device includes a connector unit and a signal capture unit. The connector unit is configured to receive the trigger signal, and transmit the same to the host. The signal capture unit is configured to capture the trigger signal, and control the display panel according to the trigger signal while the connector unit is transmitting the trigger signal to the host.
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公开(公告)号：US20230409428A1
公开(公告)日：2023-12-21
申请号：US18314128
申请日：2023-05-08
发明人： Kui RONG , Hua ZENG , Mingrui LI
IPC分类号： G06F11/14 , G06F9/4401
CPC分类号： G06F11/1417 , G06F2201/86 , G06F9/4401
摘要： A boot data reading system includes a storage circuit and a processor circuit. The storage circuit is configured to store first boot data and second boot data. The first boot data includes a first segment and a second segment. The second boot data includes a third segment, and the third segment corresponds to the first segment. The processor circuit is coupled to the storage circuit. The processor circuit reads the first segment and determines whether the first segment is correct or not. When the first segment is correct, the processor circuit reads the second segment and determines whether the second segment is correct or not. When the first segment is incorrect, the processor circuit reads the third segment and determines whether the third segment is correct or not.
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公开(公告)号：US11838577B2
公开(公告)日：2023-12-05
申请号：US17406011
申请日：2021-08-18
发明人： Yakun Cai , Dafei Li , Hong Chang
IPC分类号： H04N21/43 , G06F13/42 , H04N21/4363
CPC分类号： H04N21/43632 , G06F13/4282 , G06F2213/0042
摘要： An audio and video transmission system includes a multimedia device. The multimedia device includes a high-definition multimedia interface (HDMI) receiver, a first transfer circuit, and a first universal serial bus type C (USB-C) interface. The first transfer circuit is configured to transfer a first audio signal output by an audio channel pin of the HDMI receiver into a second audio signal in a universal serial bus (USB) interface format. The first USB-C interface is configured to transmit the second audio signal. The HDMI audio channel pin is an audio return channel (ARC) pin or an enhanced ARC pin.
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57.发明授权公开(公告)号：US11836376B2
公开(公告)日：2023-12-05
申请号：US17844783
申请日：2022-06-21
发明人： Yi-Lin Shie , Wen-Tsai Liao , Lili Tan
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0673
摘要： A convolution time de-interleaver includes an input buffer, an output buffer, a memory, an input control circuit, an output control circuit, and a controller. The memory includes a plurality of memory blocks. The input control circuit sequentially outputs a plurality of entries of data to a plurality of input register unit groups of the input buffer respectively and correspondingly. After a predetermined amount of data have been written to the input buffer, the controller writes part of data stored in the input buffer to a corresponding memory block. After the plurality of memory blocks are written, the controller writes data stored in a corresponding memory block to the output buffer. The output control circuit sequentially outputs a plurality of pieces of data stored in a plurality of output register unit groups of the output buffer.
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58.发明公开公开(公告)号：US20230376319A1
公开(公告)日：2023-11-23
申请号：US18149653
申请日：2023-01-03
发明人： Chao-Min LAI , Chien-Liang CHEN , Ming-Tsung TSAI
IPC分类号： G06F9/4401 , G06F1/10
摘要： An electronic system includes a main chip, a non-volatile storage circuit, and a detector circuit. The main chip is configured to read first time of a clock circuit. The non-volatile storage circuit is coupled to the main chip. The main chip stores the first time into the non-volatile storage circuit. The detector circuit includes a first output terminal. The first output terminal is coupled to the main chip. When a cold boot event occurs, the main chip reads the first time from the non-volatile storage circuit, and determines a reason of the cold boot event according to the first time, a second time of the clock circuit, and a logic value at the first output terminal.
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公开(公告)号：US20230360683A1
公开(公告)日：2023-11-09
申请号：US17735142
申请日：2022-05-03
发明人： GER-CHIH CHOU , CHIH-WEI CHANG , LI-JUN GU , CHUN-CHI YU , FU-CHIN TSAI
CPC分类号： G11C7/222 , G11C7/1066 , G11C7/1093 , G11C8/18
摘要： The present disclosure discloses a memory access interface device. A data processing circuit receives a data signal including 2M pieces of data from a memory device. A sampling clock generation circuit receives a data strobe signal from the memory device to generate a valid data strobe signal having P valid strobe pulses and further generate a sampling clock signal accordingly, in which P is larger than M. A sampling circuit samples the data signal according to the sampling clock signal to generate sampling results. A control circuit determines valid sampling results according to a time difference between the valid data strobe signal and the data signal and outputs valid data generated according to the valid sampling results as a read data signal to a memory access controller.
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公开(公告)号：US20230353261A1
公开(公告)日：2023-11-02
申请号：US18125508
申请日：2023-03-23
发明人： WEI-CHIEH HUANG , KUN-CHIEN HUNG
IPC分类号： H04B17/318 , H03M1/18
CPC分类号： H04B17/318 , H03M1/185
摘要： A method for measuring power of a received signal includes the following steps: determining N type(s) of sampling rate(s) of an analog-to-digital converter (ADC) according to a theoretical minimum sampling rate of the received signal; using the ADC to sample the received signal according to the N type(s) of sampling rate(s) within a period of sampling time and thereby obtaining sampling results; and measuring the power of the received signal according to the sampling results and the period of sampling time, wherein the theoretical minimum sampling rate is corresponding to a signal cycle of the received signal, the N is a positive integer, the N type(s) of sampling rate(s) is/are corresponding to N type(s) of sampling cycle(s), and any of the N type(s) of sampling cycle(s) and the signal cycle are coprime.
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