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    METHOD AND SYSTEM FOR PROVIDING INFORMATION ABOUT A TARGET OBJECT IN A FORMATTED OUTPUT SIGNAL
    51.
    发明申请
    METHOD AND SYSTEM FOR PROVIDING INFORMATION ABOUT A TARGET OBJECT IN A FORMATTED OUTPUT SIGNAL 审中-公开

    公开(公告)号：US20170219662A1

    公开(公告)日：2017-08-03

    申请号：US15010453

    申请日：2016-01-29

    Applicant: Allegro Microsystems, LLC

    Inventor： Seth Prentice ,  Andrea Foletto ,  Marcus Hagn

    IPC: G01R33/07

    CPC classification number: G01R33/07 ,  G08B25/045 ,  H03K5/08 ,  H03K7/08

    Abstract: The present disclosure is directed to methods and systems for providing information about a target based on pulse widths. The information can be provided in a formatted output signal which uses a pulse width protocol to code information by varying amplitudes and widths of successive pulses in an output signal pulse train portion. The method includes detecting a first feature of the target and in response to detecting the first feature, generating an output signal pulse train portion comprising two or more pulses with at least two of the pulses having different amplitudes and each of the two or more pulses having a width corresponding to a logic value. The widths of the two or more pulses in the output signal pulse train portion can be measured in response to the detected first feature reaching a first amplitude threshold, whereby the widths can correspond to different logic values.

    SEQUENCED PULSE-WIDTH ADJUSTMENT IN A RESONANT CLOCKING CIRCUIT
    53.
    发明申请
    SEQUENCED PULSE-WIDTH ADJUSTMENT IN A RESONANT CLOCKING CIRCUIT 审中-公开

    公开(公告)号：US20170207772A1

    公开(公告)日：2017-07-20

    申请号：US15479420

    申请日：2017-04-05

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Thomas J. Bucelot ,  Phillip J. Restle ,  David Wen-Hao Shan

    IPC: H03K3/012 ,  G06F1/08 ,  H03K7/08

    CPC classification number: H03K3/012 ,  G06F1/08 ,  G06F1/10 ,  H03K5/06 ,  H03K7/08 ,  H03K9/08

    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.

    Digital clock-duty-cycle correction
    54.
    发明授权
    Digital clock-duty-cycle correction 有权

    公开(公告)号：US09692403B2

    公开(公告)日：2017-06-27

    申请号：US14927929

    申请日：2015-10-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mohammad Elbadry

    IPC: H03K3/017 ,  H03K7/08

    CPC classification number: H03K7/08 ,  H03K5/1565

    Abstract: A clock generator includes a duty cycle correction circuit. The duty cycle correction circuit includes a duty cycle detector. The duty cycle detector, includes a first programmable delay element and a controller. The first programmable delay element is configured to delay a clock signal. The controller is configured to vary an amount of delay applied to the clock signal by the first programmable delay element, and to apply a delayed version of the clock signal, provided by the first programmable delay element, to locate an edge of a different version of the clock signal and measure time during which the different version of the clock is high. The controller is also configured to generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on measured time during which the different version of the clock is high.

    METHOD AND APPARATUS FOR RADIO MODULATOR AND ANTENNA DRIVER
    55.
    发明申请
    METHOD AND APPARATUS FOR RADIO MODULATOR AND ANTENNA DRIVER 有权

    公开(公告)号：US20170180013A1

    公开(公告)日：2017-06-22

    申请号：US14978652

    申请日：2015-12-22

    Applicant: Intel IP Corporation

    Inventor： Sathish K. Kuttan ,  Jean-Yves Michel

    IPC: H04B5/00 ,  H04B1/04 ,  H04L25/49

    CPC classification number: H04B5/0081 ,  H03F3/24 ,  H03K7/08 ,  H04B1/0458 ,  H04B1/0475 ,  H04B5/0031 ,  H04B5/0075 ,  H04B2001/0408 ,  H04L25/4902

    Abstract: A communication device includes a pulse width modulator that is provided with an oscillator signal at a communication carrier frequency. The pulse width modulator input is an amplified reference voltage that is regulated by a feedback loop. A modulation control provides the data signal to be transmitted. The modulation control may either be provided to the amplifier mixed with the reference voltage or may be provided to the pulse width modulator. A power transistor receives the pulse width modulator output and generates a chip output signal. An external filter is connected at the chip output to filter the signal that is provided to the communication antenna and produce a carrier sinusoid with an amplitude proportional to the pulse width modulated by voltage regulation and by the modulating data input. The power source is connected to the external filter. A differential version includes differential outputs from the pulse width modulator to two power transistors and through two external filters to a differential antenna.

    Active pulse positioning modulator
    58.
    再颁专利
    Active pulse positioning modulator 有权

    公开(公告)号：USRE46419E1

    公开(公告)日：2017-05-30

    申请号：US14282756

    申请日：2014-05-20

    Applicant: INTERSIL AMERICAS INC.

    Inventor： Robert H. Isham ,  Weihong Qiu

    IPC: G05F1/40

    CPC classification number: H03K7/08 ,  H02M3/156 ,  H02M3/1584 ,  H03K7/04

    Abstract: An adaptive pulse positioning modulator including a sense circuit which provides a compensation signal indicative of output voltage error, a filter circuit having an input receiving the compensation signal and an output providing an adjust signal, a leading ramp circuit which provides a repetitive first leading edge ramp signal having a slope which is adjusted by the adjust signal, a comparator circuit which provides a first start trigger signal when the first leading edge ramp signal reaches the compensation signal and a first end trigger signal when a first trailing edge ramp signal reaches the compensation signal, a trailing ramp circuit which initiates ramping of the first trailing edge ramp signal when the first start trigger signal is provided, and a pulse control logic which asserts pulses on a PWM signal based on the trigger signals.

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