公开(公告)号：US6161000A

公开(公告)日：2000-12-12

申请号：US328598

申请日：1999-06-10

Applicant: Fuji Yang ,  Pierre Genest ,  Eric Dussauby ,  Corinne Berland ,  Arnaud Maecker

Inventor： Fuji Yang ,  Pierre Genest ,  Eric Dussauby ,  Corinne Berland ,  Arnaud Maecker

IPC: H04B7/26 ,  H03C3/09 ,  H03D7/16 ,  H03L7/16 ,  H03L7/23 ,  H01Q11/12

CPC classification number: H03C3/0925 ,  H03C3/0966 ,  H03D7/163 ,  H03L7/16 ,  H03L7/23

Abstract: A transmit-receive system includes a phase-locked loop and a translation frequency loop. To bring about frequency hops, the frequencies in the two loops are varied with large increments in opposite directions. It is shown that the noise caused by the frequency division in the loops is thereby reduced.

Abstract translation: 发射 - 接收系统包括锁相环和平移频率环。 为了产生跳频，两个回路中的频率以相反的方向以大增量变化。 结果表明，由于环路中的分频引起的噪声因此降低。

公开(公告)号：US6091303A

公开(公告)日：2000-07-18

申请号：US286857

申请日：1999-04-06

Applicant: Paul W. Dent

Inventor： Paul W. Dent

IPC: H03L7/22 ,  H03C3/09 ,  H03C5/00 ,  H03L7/087 ,  H03L7/23 ,  H04B1/04 ,  H04L27/20 ,  H03C1/00 ,  H03C3/00 ,  H03L7/07 ,  H03L7/16 ,  H04L27/00

CPC classification number: H03C3/0966 ,  H03C5/00 ,  H03L7/0805 ,  H03L7/23 ,  H04L27/2014

Abstract: A circuit for reducing phase noise in a transmitted radio signal includes a first phase-locked loop circuit including a first controlled oscillator generating a first output signal at a first desired frequency, and a first phase comparator developing a first phase error signal to control the first controlled oscillator, the first error signal representative of phase differences between the first output signal and the first desired frequency. A second phase-locked loop circuit includes a second controlled oscillator generating a second output signal at a desired frequency of transmission related to the first desired frequency, and a second phase comparator developing a second phase error signal representative of phase differences between the first output signal and the desired frequency of transmission. A summer combines the first and second error signals to control the second controlled oscillator to thereby reduce, or cancel, phase noise generated by the first controlled oscillator in the second output signal transmitted as a radio signal at the desired frequency of transmission.

Abstract translation: 用于减少所发送的无线电信号中的相位噪声的电路包括第一锁相环电路，其包括产生第一期望频率的第一输出信号的第一受控振荡器，和形成第一相位误差信号以控制第一相位误差信号的第一相位比较器 控制振荡器，第一误差信号表示第一输出信号和第一期望频率之间的相位差。 第二锁相环电路包括第二受控振荡器，以与所述第一期望频率相关的期望的传输频率产生第二输出信号，以及第二相位比较器，产生表示所述第一输出信号之间的相位差的第二相位误差信号 和所需的传输频率。 夏天组合第一和第二误差信号以控制第二受控振荡器，从而减少或消除由作为无线电信号以期望的传输频率发送的第二输出信号中的第一受控振荡器产生的相位噪声。

公开(公告)号：US6028493A

公开(公告)日：2000-02-22

申请号：US64227

申请日：1998-04-21

Applicant: Christian V. Olgaard ,  Benny Madsen

Inventor： Christian V. Olgaard ,  Benny Madsen

IPC: H03C3/09 ,  H04L27/20 ,  H03C3/00

CPC classification number: H03C3/0983 ,  H03C3/0975 ,  H04L27/2057

Abstract: A modulation synthesizer circuit produces a fixed intermediate frequency unmodulated signal without harmonics aliasing back into the transmit spectrum, thus, eliminating the need for a bandpass filter. The modulation synthesizer circuit includes a phase shifter placed before the down conversion mixer. The phase shifter may be placed outside the modulation synthesizer loop such that the phase shifter produces quadrature carrier wave signals to the down conversion mixer. In the alternative the phase shifter may be kept within the modulation synthesizer loop and produce quadrature modulated transmit signals to the down conversion mixer. Any harmonic frequencies generated by the phase shifter are harmonics of the carrier wave signal or modulated transmit signal. Thus, with the appropriate choice of carrier wave signal or modulated transmit signal, any harmonics generated by the phase shifter can be prevented from aliasing back into the transmit spectrum and therefore need not be filtered. Consequently, the bandpass filter typically found after the quadrature modulator can be eliminated.

Abstract translation: 调制合成器电路产生固定的中频未调制信号，没有谐波混叠回发射频谱，因此不需要带通滤波器。 调制合成器电路包括放置在下变频混频器之前的移相器。 移相器可以放置在调制合成器环路外部，使得移相器产生到下变频混频器的正交载波信号。 在替代方案中，移相器可以保持在调制合成器环路内并且产生到下变频混频器的正交调制发射信号。 由移相器产生的任何谐波都是载波信号或调制发射信号的谐波。 因此，通过适当选择载波信号或调制发射信号，可以防止由移相器产生的任何谐波混叠回发射频谱，因此不需要滤波。 因此，可以消除通常在正交调制器之后发现的带通滤波器。

公开(公告)号：US06018275A

公开(公告)日：2000-01-25

申请号：US993268

申请日：1997-12-18

Applicant: Alan Christopher Perrett ,  Kenneth Peter Mason

Inventor： Alan Christopher Perrett ,  Kenneth Peter Mason

IPC: H03C3/09 ,  H03C3/00 ,  H04L27/04 ,  H04L27/12 ,  H04L27/20

CPC classification number: H03C3/0983 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0966 ,  H03C3/0975

Abstract: A transmitter and a phase locked loop (30) for a transmitter are disclosed. The phase locked loop (30) upconverts the frequency of a baseband signal to a frequency for radio transmission. As well as the usual components, the phase locked loop (30) comprises a modulator (39) for modulating a baseband signal (f.sub.bb) onto a carrier (f.sub.ref /R) and forwarding the resultant modulated signal (f.sub.c) to one of the inputs of the phase detector (33). It also comprises a low pass filter (38) in its forward path between the phase detector (33) and the voltage controlled oscillator (34) for passing signals having baseband signal frequencies. A mixer (35) and main frequency divider (36) are provided in the feedback path to downconvert the transmit signal (f.sub.tx). This low division eliminates large amounts of multiplicative noise within the loop bandwidth, and therefore enables a large loop bandwidth to be used. Consequently, the settling time of the phase locked loop is improved.

Abstract translation: 公开了用于发射机的发射机和锁相环（30）。 锁相环（30）将基带信号的频率上变频到无线电传输的频率。 除了通常的组件之外，锁相环（30）包括用于将基带信号（fbb）调制到载波（fref / R）上的调制器（39），并将所得到的调制信号（fc）转发到输入 的相位检测器（33）。 它还包括在相位检测器（33）和压控振荡器（34）之间的正向通路中的低通滤波器（38），用于通过具有基带信号频率的信号。 在反馈路径中设置混频器（35）和主分频器（36），以对发射信号（ftx）进行下变频。 该低分频消除环路带宽内的大量乘法噪声，因此能够使用较大的环路带宽。 因此，提高了锁相环的稳定时间。

公开(公告)号：US5905388A

公开(公告)日：1999-05-18

申请号：US860670

申请日：1997-09-26

Applicant: Robertus L. Van Der Valk ,  Robertus J. Dequesnoy ,  Johannes H. A. De Rijk ,  Menno T. Spijker

Inventor： Robertus L. Van Der Valk ,  Robertus J. Dequesnoy ,  Johannes H. A. De Rijk ,  Menno T. Spijker

IPC: H03C1/60 ,  H03C1/50 ,  H03C3/09 ,  H03L7/18 ,  H04L27/36 ,  H03B21/00 ,  G06F1/16 ,  H03L7/06

CPC classification number: H03C3/0975 ,  H03C1/50 ,  H03C3/0966 ,  H03L7/1806

Abstract: The invention relates to a circuit for frequency synthesis, comprising: a digital controlled oscillator, comprising (a) a clock generator; an accumulator circuit to which the signal from the clock generator is fed; and a control digit feed circuit for feeding to the digital oscillator a signal representing a control digit; and (b) a phase-locked loop which is connected to the carry output terminal of the accumulator circuit and which is provided with a phase detector, a low-pass filter and a controlled oscillator, wherein the carry output terminal is connected to the phase detector. The digital controlled oscillator is preferable adapted to generate a signal representing a remainder, wherein a correction circuit is arranged for deriving a correction signal from the remainder. The correction circuit is connected to a combination circuit connected to one of the inputs of the phase detector or to a combination circuit incorporated in the phase-locked loop. The circuits can also be connected in cascade.

Abstract translation: PCT No.PCT / NL96 / 00013 Sec。 371日期：1997年9月26日 102（e）1997年9月26日PCT PCT 1996年1月8日PCT公布。 WO96 / 21279 PCT公开号 日期1996年7月11日本发明涉及一种用于频率合成的电路，包括：数字控制振荡器，包括：（a）时钟发生器; 来自时钟发生器的信号被馈送到的累加器电路; 以及控制数字进给电路，用于向数字振荡器馈送表示控制数字的信号; 和（b）锁相环，其连接到蓄电池电路的进位输出端，并且具有相位检测器，低通滤波器和受控振荡器，其中进位输出端子连接到相位 探测器。 数字控制振荡器优选地适于产生表示余数的信号，其中校正电路被布置用于从其余部分导出校正信号。 校正电路连接到连接到相位检测器的一个输入端的组合电路，或连接到并入锁相环路的组合电路。 电路也可以级联连接。

公开(公告)号：US5898906A

公开(公告)日：1999-04-27

申请号：US738607

申请日：1996-10-29

Applicant: Anthony David Williams

Inventor： Anthony David Williams

IPC: H03C3/09 ,  H03C3/40 ,  H03D7/16 ,  H04B1/40

CPC classification number: H04B1/405 ,  H03C3/0908 ,  H03C3/40 ,  H03D7/163

Abstract: A system and method for implementing a cellular radio transmitter device comprises a first oscillator device for generating a first oscillator output signal, a second oscillator device for generating a second oscillator output signal, a power amplifier for amplifying the second oscillator output signal to obtain a transmit signal, a mixer device for combining the first oscillator output signal and the transmit signal to produce a mixer output signal, a phase comparator for comparing the mixer output signal and a transmitter input signal and responsively generating a control signal to control the transmit oscillator, and a feedback path for adding the mixer output signal to the transmitter input signal to compensate for distortion present in the transmit signal.

Abstract translation: 用于实现蜂窝无线电发射机设备的系统和方法包括：用于产生第一振荡器输出信号的第一振荡器装置，用于产生第二振荡器输出信号的第二振荡器装置，用于放大第二振荡器输出信号以获得发射 信号，用于组合第一振荡器输出信号和发射信号以产生混频器输出信号的混频器装置，用于比较混频器输出信号和发射机输入信号并响应地产生控制信号以控制发射振荡器的相位比较器，以及 用于将混频器输出信号添加到发射机输入信号以补偿存在于发射信号中的失真的反馈路径。

公开(公告)号：US5889443A

公开(公告)日：1999-03-30

申请号：US926756

申请日：1997-09-10

Applicant: Klaus J.o slashed.rgensen

Inventor： Klaus J.o slashed.rgensen

IPC: H03C3/09 ,  H03L7/193 ,  H03L7/197 ,  H04L27/12 ,  H03C3/00

CPC classification number: H03C3/0958 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03L7/193 ,  H03L7/197 ,  H04L27/12

Abstract: A frequency synthesizing circuit has an input on which a bit flow is received, and an output on which a data-modulated output signal is supplied. The circuit moreover comprises a crystal oscillator supplying a reference clock signal, a phase-locked loop (PLL) having a VCO and a phase detector. The phase detector compares the data-modulated output signal with the reference clock signal and, in response to this, supplies an error signal by means of which the VCO output frequency is controlled. A compensation circuit, which receives a measure of the bit flow received, compensates the data-modulated output signal in the phase-locked loop in response to this before it is supplied to the phase detector.

Abstract translation: 频率合成电路具有接收位流的输入和提供数据调制输出信号的输出。 该电路还包括提供参考时钟信号的晶体振荡器，具有VCO的锁相环（PLL）和相位检测器。 相位检测器将数据调制输出信号与参考时钟信号进行比较，并且响应于此，提供控制VCO输出频率的误差信号。 接收到接收到的比特流的量度的补偿电路在被提供给相位检测器之前，根据该补偿电路补偿锁相环中的数据调制输出信号。

公开(公告)号：US5872807A

公开(公告)日：1999-02-16

申请号：US799914

申请日：1997-02-13

Applicant: James Ronald Booth ,  Donald Reid Bush ,  John Thomas Fessler ,  Keith Bryan Hardin

Inventor： James Ronald Booth ,  Donald Reid Bush ,  John Thomas Fessler ,  Keith Bryan Hardin

IPC: G06F15/78 ,  G06F1/04 ,  H03B29/00 ,  H03C3/09 ,  H03K4/94 ,  H03L7/07 ,  H03L7/08 ,  H03L7/087 ,  H03L7/18 ,  H03L7/197 ,  H04J13/00 ,  H04B15/00

CPC classification number: H03C3/0966 ,  H03B29/00 ,  H03C3/0925 ,  H03C3/0941 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/087 ,  H03L7/18 ,  H03L7/197 ,  H04B2215/064 ,  H04B2215/067

Abstract: A clock circuit includes an oscillator for generating a reference frequency signal, and a spread spectrum clock generator cooperating with the oscillator for generating a spread spectrum clock output signal having a fundamental frequency and reduced amplitude EMI spectral components at harmonics of the fundamental frequency. The spread spectrum clock generator preferably includes a clock pulse generator for generating a series of clock pulses, and a spread spectrum modulator for frequency modulating the clock pulse generator to broaden and flatten amplitudes of EMI spectral components which would otherwise be produced by the clock pulse generator. The spread spectrum modulator frequency modulates the clock pulses with specific profiles of frequency deviation versus the period of the profile. Electronic devices including the spread spectrum clock circuit and associated method are also disclosed.

公开(公告)号：US5867524A

公开(公告)日：1999-02-02

申请号：US800890

申请日：1997-02-13

Applicant: James Ronald Booth ,  Donald Reid Bush ,  John Thomas Fessler ,  Keith Bryan Hardin

Inventor： James Ronald Booth ,  Donald Reid Bush ,  John Thomas Fessler ,  Keith Bryan Hardin

IPC: G06F15/78 ,  G06F1/04 ,  H03B29/00 ,  H03C3/09 ,  H03K4/94 ,  H03L7/197 ,  H04B15/00

CPC classification number: H03C3/0966 ,  H03B29/00 ,  H03C3/0925 ,  H03C3/0941 ,  H03L7/0805 ,  H03L7/197 ,  H04B2215/064 ,  H04B2215/067

Abstract: A clock circuit includes an oscillator for generating a reference frequency signal, and a spread spectrum clock generator cooperating with the oscillator for generating a spread spectrum clock output signal having a fundamental frequency and reduced amplitude EMI spectral components at harmonics of the fundamental frequency. The spread spectrum clock generator preferably includes a clock pulse generator for generating a series of clock pulses, and a spread spectrum modulator for frequency modulating the clock pulse generator to broaden and flatten amplitudes of EMI spectral components which would otherwise be produced by the clock pulse generator. The spread spectrum modulator frequency modulates the clock pulses with specific profiles of frequency deviation versus the period of the profile. Electronic devices including the spread spectrum clock circuit and associated method are also disclosed.

Abstract translation: 时钟电路包括用于产生参考频率信号的振荡器和与振荡器协作的扩展频谱时钟发生器，用于产生具有在基频的谐波处的基频和降低幅度的EMI频谱分量的扩频时钟输出信号。 扩频时钟发生器优选地包括用于产生一系列时钟脉冲的时钟脉冲发生器和用于对时钟脉冲发生器进行频率调制的扩展频谱调制器，以扩大和平缓由EMI时钟脉冲发生器产生的EMI频谱分量的幅度 。 扩频调制器利用频率偏差的特性曲线与轮廓周期调制时钟脉冲。 还公开了包括扩频时钟电路和相关方法的电子设备。

公开(公告)号：US5834987A

公开(公告)日：1998-11-10

申请号：US902836

申请日：1997-07-30

Applicant: Paul Wilkinson Dent

Inventor： Paul Wilkinson Dent

IPC: H03C3/09 ,  H03L7/197 ,  H03C3/00 ,  H03C1/00 ,  H03K7/02 ,  H03L7/18

CPC classification number: H03C3/0975 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0966 ,  H03L7/1974 ,  H03L7/1976

Abstract: A frequency synthesizer includes a controlled oscillator which is responsive to a frequency control input signal, to generate an output frequency. A programmable frequency divider is responsive to the output frequency and to a divider control input, to divide the output frequency by a first integral ratio or by a second integral ratio in response to the divider control input, to thereby produce a divided signal. A phase comparator is responsive to a reference frequency signal and to the divided signal, to compare the reference frequency signal and the divided signal, and thereby produce a first error signal. A sigma-delta modulator is responsive to a modulation input to produce the divider control input. A loop filter is responsive to the first error signal, to thereby produce the frequency control input signal. Ripple compensation signals and direct modulation signals may also be provided, to provide a three-point modulator for a frequency synthesizer. Analog and digital embodiments may also be provided.

Abstract translation: 频率合成器包括响应于频率控制输入信号的受控振荡器，以产生输出频率。 可编程分频器响应于输出频率和分频器控制输入，以响应于分频器控制输入将输出频率除以第一积分比或第二积分比，从而产生分频信号。 相位比较器响应于参考频率信号和分频信号，以比较参考频率信号和分频信号，从而产生第一误差信号。 Σ-Δ调制器响应于调制输入以产生除法器控制输入。 环路滤波器响应于第一误差信号，从而产生频率控制输入信号。 还可以提供纹波补偿信号和直接调制信号，以提供用于频率合成器的三点调制器。 还可以提供模拟和数字实施例。