公开(公告)号：US5570380A

公开(公告)日：1996-10-29

申请号：US346601

申请日：1994-11-29

Applicant: Paolo Gadducci ,  David Moloney ,  Giorgio Betti

Inventor： Paolo Gadducci ,  David Moloney ,  Giorgio Betti

IPC: G11B20/14 ,  G11B20/10 ,  G11B20/18 ,  H04B15/00 ,  G06F11/00

CPC classification number: G11B20/10009 ,  G11B20/1426

Abstract: A survival sequence register for a read channel employing a variable threshold peak qualification technique, has a first data shift register receiving a logic sum stream of two serial streams of coded digital data, corresponding to qualified peaks detected by a reading pick-up of positive and negative sign, respectively, and a pointer register. A control circuit generates an erase signal when an incoming pulse is recognized as corresponding to a detected peak of the same sign of the previously detected peak. The erase signal is input to logic gates which each drive a reset terminal of a flip-flop of the data shift register, with the exception of the first flip-flop of the register. The pointer register being reset when the control circuit receives a pulse corresponding to a peak of opposite polarity of the detected peak relative to the preceding pulse.

Abstract translation: 采用可变阈值峰值鉴定技术的读通道的存活序列寄存器具有第一数据移位寄存器，其接收编码数字数据的两个串行数据流的逻辑和流，对应于由读取拾取器检测到的合格峰值， 分别为负号和指针寄存器。 当输入脉冲被识别为对应于先前检测到的峰值的相同符号的检测到的峰值时，控制电路产生擦除信号。 除了寄存器的第一触发器之外，擦除信号被输入到逻辑门，每个逻辑门驱动数据移位寄存器的触发器的复位端。 当控制电路接收到相对于先前脉冲的检测到的峰值的极性相反的峰值的脉冲时，指针寄存器被复位。

公开(公告)号：US5570057A

公开(公告)日：1996-10-29

申请号：US420756

申请日：1995-04-12

Applicant: Sergio Palara

Inventor： Sergio Palara

IPC: H05B41/24 ,  H02M1/08 ,  H02M7/537 ,  H03K17/30 ,  H03K17/567 ,  H03K17/00

CPC classification number: H03K17/567 ,  H03K17/30

Abstract: A three-terminal insulated-gate power electronic device includes a first, bipolar power transistor and a second, insulated-gate transistor forming a darlington pair. The bipolar power transistor has a first electrode, a second electrode, and a control electrode respectively connected to a first electrode of the insulated-gate transistor and to a first external terminal of the three-terminal device, to a second external terminal of the three-terminal device, and to one second electrode of the insulated-gate transistor. The three-terminal device further includes switching means connected between the control electrode and the second electrode of the bipolar power transistor, and control circuit means connected to another second electrode of the insulated-gate transistor and controlling the switching means to switch it from a highly-conducting condition for low values of a current flowing through the first and second external terminals to a non-conducting condition for high values of the current flowing between the first and second external terminals.

Abstract translation: 三端绝缘栅功率电子器件包括第一双极功率晶体管和形成达林顿对的第二绝缘栅晶体管。 双极功率晶体管具有分别连接到绝缘栅晶体管的第一电极和三端子器件的第一外部端子的第一电极，第二电极和控制电极连接到三极管的第二外部端子 - 端子器件，以及绝缘栅晶体管的一个第二电极。 三端子装置还包括连接在控制电极和双极功率晶体管的第二电极之间的开关装置，以及连接到绝缘栅晶体管的另一个第二电极的控制电路装置，并且控制开关装置将其从高度 在第一外部端子和第二外部端子之间流过电流的高值的情况下，流过第一和第二外部端子的电流的低值的导通条件成为非导通状态。

公开(公告)号：US5565806A

公开(公告)日：1996-10-15

申请号：US262590

申请日：1994-06-20

Applicant: Paolo Cordini ,  Giorgio Pedrazzini ,  Domenico Rossi

Inventor： Paolo Cordini ,  Giorgio Pedrazzini ,  Domenico Rossi

IPC: H03K19/018 ,  G06J1/00 ,  H03F3/62 ,  H03F3/68 ,  H03B1/00

CPC classification number: H03F3/62 ,  G06J1/00

Abstract: The present invention relates to an integrated input/output interface for low and/or high voltage range signals of the digital and/or analog type. It comprises essentially a power amplification circuit block (2) having at least one low voltage range input terminal (A) and at least one high voltage range output terminal (B), and a second amplification circuit block (3) having a high voltage range input terminal connected to said high voltage range output terminal (B) and at least one low voltage range output terminal (D). A conventional circuit block (4) prevents a high voltage range signal being input to said high voltage range terminal (B) from propagating through the first power amplification circuit block (2), so that it only affects the second amplification circuit block (3). This interface is implemented in mixed high voltage bipolar/CMOS/DMOS technology.

Abstract translation: 本发明涉及用于数字和/或模拟类型的低和/或高电压范围信号的集成输入/输出接口。 它基本上包括具有至少一个低电压范围输入端（A）和至少一个高电压范围输出端（B）的功率放大电路块（2）和具有高电压范围的第二放大电路块（3） 输入端子连接到所述高压范围输出端子（B）和至少一个低电压范围输出端子（D）。 常规电路块（4）防止输入到所述高电压范围端子（B）的高电压范围信号传播通过第一功率放大电路块（2），从而仅影响第二放大电路块（3） 。 该接口采用混合高压双极/ CMOS / DMOS技术实现。

公开(公告)号：US5563826A

公开(公告)日：1996-10-08

申请号：US422813

申请日：1995-04-17

Applicant: Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone

Inventor： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/24 ,  G11C16/28 ,  G11C7/06

CPC classification number: G11C16/28 ,  G11C16/24

Abstract: A read circuit comprises at least one array branch connected to at least one bit line, and a reference branch connected to a reference line. The array and reference branches each comprise a precharge circuit and load interposed between the supply and the bit line and reference line respectively. The reference load is so formed as to generate a reference current which, during evaluation, is twice the current supplied to the bit line. The reference line is connected to an extra-current transistor which is only turned on during equalization so that, during equalization, the selected bit line is supplied with a high current approximating that supplied to the reference line. As such, if the cell to be read is written, the output voltage of the array branch is brought rapidly to its natural high value; whereas, if the cell to be read is erased, the output voltage may return to its low value when the extra-current transistor is turned off, thus permitting reading in advance.

Abstract translation: 读取电路包括连接到至少一个位线的至少一个阵列分支和连接到参考线的参考分支。 阵列和参考支路各自包括预充电电路和插入在电源和位线和参考线之间的负载。 参考负载被形成为产生参考电流，其在评估期间是提供给位线的电流的两倍。 参考线连接到在均衡期间仅导通的过电流晶体管，使得在均衡期间，所选择的位线被提供近似于提供给参考线的高电流。 因此，如果要读取的单元被写入，则阵列分支的输出电压迅速地达到其自然的高值; 而如果要读取的单元被擦除，则当超级晶体管截止时，输出电压可能返回到其低电平值，因此可以预先读取。

公开(公告)号：US5553067A

公开(公告)日：1996-09-03

申请号：US319951

申请日：1994-10-07

Applicant: Christopher P. H. Walker ,  Peter W. Thompson

Inventor： Christopher P. H. Walker ,  Peter W. Thompson

IPC: G06F11/10 ,  B29C65/36 ,  B29C65/66 ,  B29C65/68 ,  H03M9/00 ,  H03M13/09 ,  H04L1/00 ,  H04J3/24

CPC classification number: H04L1/0083 ,  H03M13/093

Abstract: A scheme for altering checking information in a message packet intended to be transmitted between computers is described. In this scheme, when an information portion of the packet is altered, checking bits contained in the packets are altered in dependence only on the set of checking bits in the message packet before modification of the information portion and on the modifications to the information portion. Thus, it is not necessary to generate new checking bits from a modified information portion.

Abstract translation: 描述了用于改变计算机之间要发送的消息包中的检查信息的方案。 在该方案中，当分组的信息部分被改变时，检查包中包含的比特是根据在修改信息部分之前的消息包中的一组检查比特和对该信息部分的修改而改变的。 因此，不需要从修改的信息部分生成新的检查位。

公开(公告)号：US5552747A

公开(公告)日：1996-09-03

申请号：US457759

申请日：1995-06-01

Applicant: Luciano Tomasini ,  Rinaldo Castello ,  Pierangelo Confalonieri

Inventor： Luciano Tomasini ,  Rinaldo Castello ,  Pierangelo Confalonieri

IPC: H03K17/06 ,  H03K17/687 ,  G05F1/10 ,  G05F3/02

CPC classification number: H03K17/063

Abstract: A driver circuit, for an electronic switch which is to be operated from a clock signal, comprises an inverter driven by the clock signal, and a voltage doubler which is connected to supply the inverter and connected to be driven by the complementary clock signal.

Abstract translation: 用于从时钟信号操作的电子开关的驱动电路包括由时钟信号驱动的反相器，以及连接以提供反相器并连接以由互补时钟信号驱动的倍压器。

公开(公告)号：US5534448A

公开(公告)日：1996-07-09

申请号：US282408

申请日：1994-07-28

Applicant: Livio Baldi

Inventor： Livio Baldi

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A process for forming low threshold voltage P-channel MOS transistors in semiconductor integrated circuits for analog applications, said circuits including high resistivity resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-type well, comprises the steps of,providing a first mask over both said resistors and the semiconductor regions where the low threshold voltage P-channel transistors are to be formed,doping the polycrystalline layer uncovered by said first mask,--providing a second mask for protecting the resistors and the semiconductor regions where said low threshold voltage P-channel transistors are to be formed, andN+ implanting the active areas of the N-channel transistors.

Abstract translation: 一种用于在用于模拟应用的半导体集成电路中形成低阈值电压P沟道MOS晶体管的工艺，所述电路包括形成在多晶硅层中的高电阻率电阻器和具有有源区域的N沟道MOS晶体管，所述有源区域已经通过 P型阱包括以下步骤：在所述电阻器和要形成低阈值电压P沟道晶体管的半导体区域上提供第一掩模，掺杂由所述第一掩模未覆盖的多晶层， - 提供第二掩模 用于保护要形成所述低阈值电压P沟道晶体管的电阻器和半导体区域的掩模，以及N +注入N沟道晶体管的有源区。

公开(公告)号：US5528536A

公开(公告)日：1996-06-18

申请号：US344232

申请日：1994-11-23

Applicant: Livio Baldi ,  Federico Pio

Inventor： Livio Baldi ,  Federico Pio

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C5/14

CPC classification number: G11C16/30 ,  G11C16/12

Abstract: A programming voltage is supplied to a control gate of a non-volatile memory cell via a control gate line. A supply voltage is coupled to a first plate of a capacitor and a reference voltage is coupled to a second plate of the capacitor. The supply voltage is then uncoupled from the first plate and the reference voltage is uncoupled from the second plate. Next, the reference voltage is coupled to the first plate to generate the programming voltage on the second plate.

Abstract translation: 编程电压通过控制栅极线提供给非易失性存储单元的控制栅极。 电源电压耦合到电容器的第一板，参考电压耦合到电容器的第二板。 然后将电源电压与第一板分离，并且参考电压与第二板脱离。 接下来，参考电压耦合到第一板以在第二板上产生编程电压。

公开(公告)号：US5525832A

公开(公告)日：1996-06-11

申请号：US17816

申请日：1993-02-16

Applicant: Pietro Consiglio ,  Pietro Erratico

Inventor： Pietro Consiglio ,  Pietro Erratico

IPC: H01L27/08 ,  H01L27/02 ,  H01L29/10

CPC classification number: H01L27/0251

Abstract: A substrate insulation device includes power supply terminals which are connected to a terminal of an active integrated element which has, with respect to a substrate on which it is defined, at least one reverse-biased junction.

Abstract translation: 基板绝缘装置包括电源端子，其连接到有源集成元件的端子，该有源集成元件相对于限定了该基板的基板，具有至少一个反向偏置接合部。

公开(公告)号：US5521414A

公开(公告)日：1996-05-28

申请号：US234334

申请日：1994-04-28

Applicant: Sergio Palara

Inventor： Sergio Palara

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/732 ,  H01L29/78 ,  H01L23/62 ,  H01L27/082 ,  H01L29/00 ,  H01L29/76

CPC classification number: H01L27/0248 ,  H01L27/0255 ,  H01L27/0664 ,  H01L29/7808 ,  H01L2924/0002

Abstract: A structure of an electronic device having a predetermined unidirectional conduction threshold is formed on a chip of an N-type semiconductor material and includes a plurality of isolated N-type regions. Each isolated N-type region is bounded laterally by an isolating region and at the bottom by buried P-type and N-type regions which form in combination a junction with a predetermined reverse conduction threshold and means of connecting the junctions of the various isolated regions serially together. The buried N-type region of the first junction in the series is connected to a common electrode, which also is one terminal of the device, over an internal path of the N-type material of the chip, and the buried P-type region of the last junction in the series contains an additional buried N-type region which is connected electrically to a second terminal of the device.

Abstract translation: 在N型半导体材料的芯片上形成具有预定的单向导通阈值的电子器件的结构，并且包括多个隔离的N型区域。 每个隔离的N型区域被隔离区侧向限制，并且在底部由掩埋的P型和N型区组合形成具有预定反向导通阈值的结和连接各个隔离区的结的装置 串联在一起 串联的第一结的掩埋N型区域连接到公共电极，该公共电极也是器件的一个端子，在芯片的N型材料的内部路径上，并且埋入P型区域 该系列中的最后一个结点包含一个附加的掩埋的N型区域，该区域电连接到该设备的第二端子。