公开(公告)号：US20190252366A1

公开(公告)日：2019-08-15

申请号：US15951129

申请日：2018-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L27/02 ,  H01L27/11 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66

Abstract: A layout of a semiconductor device, a semiconductor device and a method of forming the same, the semiconductor device include a first fin and a second fin disposed on a substrate, a gate and a spacer. The first fin and the second fin both include two opposite edges, and the gate completely covers the two opposite edges of the first fin and only covers one sidewall of the two opposite edges of the second fin. The spacer is disposed at two sides of the gate, and the spacer covers another sidewall of the two opposite edges of the second fin.

公开(公告)号：US20190245038A1

公开(公告)日：2019-08-08

申请号：US15913533

申请日：2018-03-06

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/08 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/76224 ,  H01L27/0617 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

公开(公告)号：US10374051B1

公开(公告)日：2019-08-06

申请号：US15987891

申请日：2018-05-23

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ji-Min Lin ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Pin-Hong Chen ,  Chih-Chien Liu ,  Chun-Chieh Chiu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Yi-An Huang ,  Kai-Jiun Chang

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/43

Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a metal silicon nitride layer on the silicon layer; forming a stress layer on the metal silicon nitride layer; performing a thermal treatment process; removing the stress layer; forming a conductive layer on the metal silicon nitride layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

公开(公告)号：US10373966B2

公开(公告)日：2019-08-06

申请号：US15264423

申请日：2016-09-13

Applicant: United Microelectronics Corp.

Inventor： Po-Han Jen ,  Chieh-Yu Tsai ,  Chun-Cheng Chiang

IPC: H01L27/112 ,  H01L49/02 ,  H01L21/28

Abstract: A Mask ROM is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-Si layer including an upper horizontal bar, a lower horizontal bar contiguous with the upper horizontal bar, and a step structure with a step height at which the two bars are contiguous, a spacer on the sidewall of the step structure, and a first silicide layer on the first poly-Si layer and being divided apart by the spacer. Each second resistor includes an undoped second poly-Si layer, and a contiguous second silicide layer on the second poly-Si layer. The contact plugs are disposed on the first silicide layer on the upper horizontal bar of each first poly-Si layer, and on the second silicide layer.

公开(公告)号：US10373861B1

公开(公告)日：2019-08-06

申请号：US16026077

申请日：2018-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Ying Hsieh ,  Chih-Jung Chen ,  Chien-Hung Chen ,  Chih-Yueh Li ,  Cheng-Pu Chiu ,  Shih-Min Lu ,  Yung-Sung Lin

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.

公开(公告)号：US20190237660A1

公开(公告)日：2019-08-01

申请号：US15904429

申请日：2018-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22

Abstract: A magnetoresistive random access memory (MRAM) is provided in the present invention, including a conductive plug with a protruding portion extending outwardly on one side and a notched portion concaving inwardly on the other side of the upper edge of conductive plug, and a memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction (MTJ) on the bottom electrode, and a top electrode on the magnetic tunnel junction, wherein the bottom surface of memory cell completely overlaps the top surface of conductive plug.

公开(公告)号：US20190237468A1

公开(公告)日：2019-08-01

申请号：US15901875

申请日：2018-02-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L27/108

Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.

公开(公告)号：US20190237460A1

公开(公告)日：2019-08-01

申请号：US16380953

申请日：2019-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Ping Chen ,  Chien-Hung Chen

IPC: H01L27/06 ,  H01L27/11543 ,  H01L27/11541 ,  H01L29/788 ,  H01L21/285 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/31144 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for fabricating a semiconductor device includes the steps of providing a semiconductor substrate; forming a tunnel dielectric on the semiconductor substrate; forming a floating gate on the tunnel dielectric; forming an insulation layer conformally disposed on the top surface and the sidewall surface of the floating gate; forming a control gate disposed on the insulation layer and the floating gate; and forming a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, where the spacer overlaps portions of the top surface of the floating gate

公开(公告)号：US10366991B1

公开(公告)日：2019-07-30

申请号：US15880492

申请日：2018-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Yu-Ying Lin ,  Yen-Hsing Chen ,  Chun-Jen Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.

公开(公告)号：US10366978B1

公开(公告)日：2019-07-30

申请号：US16036914

申请日：2018-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hsiang Chang ,  Hou-Jen Chiu ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

Abstract: A grounded gate NMOS transistor includes a P-type substrate, P-well region in the P-type substrate, and a gate finger traversing the P-well region. The gate finger has a first spacer on a first sidewall and a second spacer on a second sidewall opposite to the first sidewall. An N+ drain doping region is disposed in the P-type substrate and is adjacent to the first sidewall of the gate finger. The N+ drain doping region is contiguous with a bottom edge of the first spacer. An N+ source doping region is disposed in the P-type substrate opposite to the N+ drain doping region. The N+ source doping region is kept a predetermined distance from a bottom edge of the second spacer. A P+ pick-up ring is disposed in the P-well region and surrounds the gate finger, the N+ drain doping region, and the N+ source doping region.