公开(公告)号：US5210675A

公开(公告)日：1993-05-11

申请号：US928670

申请日：1992-08-17

Applicant: Sergio Palara

Inventor： Sergio Palara

IPC: H02H9/04

CPC classification number: H02H9/047

Abstract: Circuits are provided for protecting against negative overvoltages of a power supply in an integrated circuit including a power device (P). The protection circuits include a voltage limiting device (T4) interposed between supply and control terminals of the power device, as well as a switching device (T6). The switching device is interposed between a control terminal of the voltage limiting means and ground. The switching means is controlled by the power supply to cause conduction of the voltage limiting means for firing the power device if a positive overvoltage on the supply terminal (CL) of the power device is combined with a negative overvoltage of the power supply (Vb). In some embodiments the switching device and the voltage limiting device are both NPN transistors. In other embodiments the the switching device and the voltage limiting device are both MOS transistors.

Abstract translation: 提供电路用于防止包括功率器件（P）的集成电路中的电源的负过电压。 保护电路包括插在功率器件的供电和控制端子之间的电压限制装置（T4）以及开关装置（T6）。 开关装置插在电压限制装置的控制端子和地之间。 如果电力设备的电源端子（CL）上的正过压与电源（Vb）的负过压组合，则开关装置由电源控制，以引起用于点火功率器件的电压限制装置的导通， 。 在一些实施例中，开关装置和限压装置都是NPN晶体管。 在其他实施例中，开关器件和限压器件都是MOS晶体管。

公开(公告)号：US5208527A

公开(公告)日：1993-05-04

申请号：US811261

申请日：1991-12-19

Applicant: Vanni Poletto ,  Massimiliano Brambilla

Inventor： Vanni Poletto ,  Massimiliano Brambilla

IPC: G05F3/26 ,  G05F1/46 ,  G05F3/30

CPC classification number: G05F1/463 ,  G05F3/30 ,  Y10S323/907

Abstract: The generator comprises a first generator of voltage with thermal drift of zero, a second generator of voltage with given thermal drift, first means for applying a given load to the voltage generated by the first generator, second means for applying a given load to the voltage generated by the second generator, subtracting means for subtracting one from the other the loaded voltages generated by said first and second generator of voltage.

Abstract translation: 发电机包括具有热漂移为零的电压的第一发生器，具有给定热漂移的电压的第二发生器，用于将给定负载施加到由第一发电机产生的电压的第一装置，用于将给定负载施加到电压的第二装置 由所述第二发电机产生的减法装置，用于从所述第一和第二发电机产生的负载电压中减去一个电压。

公开(公告)号：US5187452A

公开(公告)日：1993-02-16

申请号：US813154

申请日：1991-12-23

Applicant: Gianfranco Vai ,  Maurizio Zuffada ,  Fabrizio Sacchi ,  David Moloney ,  Giorgio Betti

Inventor： Gianfranco Vai ,  Maurizio Zuffada ,  Fabrizio Sacchi ,  David Moloney ,  Giorgio Betti

IPC: H03K3/017 ,  H03K3/282

CPC classification number: H03K3/017 ,  H03K3/2821

Abstract: A control circuit for an oscillator comprising a multivibrator with transistors having their emitters connected in common and being supplied corresponding currents on respective legs, comprises a circuit structure adapted to produce on output terminals, on the one side, a current which is proportional to a reference current according to a predetermined parameter, and on the other side, a second current in turn correlated to the reference current as a function of said parameter, thereby to modify the oscillator duty cycle for a given operating frequency.

Abstract translation: 一种用于振荡器的控制电路，包括多谐振荡器，其具有晶体管，其晶体管具有共同连接的发射极，并且在相应的支路上提供相应的电流，包括适于在输出端子上产生与参考电压成比例的电流的电路结构 电流，另一方面，第二电流又作为所述参数的函数与参考电流相关，从而修改给定工作频率的振荡器占空比。

公开(公告)号：US5182470A

公开(公告)日：1993-01-26

申请号：US593430

申请日：1990-10-05

Applicant: Roberto Gariboldi ,  Alberto Gola

Inventor： Roberto Gariboldi ,  Alberto Gola

IPC: H02H9/04

CPC classification number: H02H9/047

Abstract: An output stage with a protection circuit against negative overvoltage at its output terminal, having a transistor with collector output and with the emitter connected to a reference voltage line; a diode for protection against negative overvoltages present on the output is arranged between the collector and the output of the stage. In order to give the output of the stage a presettable minimum voltage level, the reference voltage line is set to a preset voltage which differs from the ground voltage. For this purpose, the circuit comprises an operational amplifier in a voltage-follower configuration, the output whereof is connected to the reference voltage line, a diode which is connected between the ground and the non-inverting terminal of the operational amplifier, and a current source which is connected between the non-inverting input of the operational amplifier and a negative supply line.

公开(公告)号：US5180927A

公开(公告)日：1993-01-19

申请号：US794939

申请日：1991-11-20

Applicant: Vanni Poletto

Inventor： Vanni Poletto

IPC: G06F1/24 ,  H03K3/00 ,  H03K17/24

CPC classification number: G06F1/24

Abstract: A microprocessor reset device comprising a first comparator which, when the input signal of the device falls below a first threshold, closes a switch controlling discharging of a condenser. A second comparator connected to the condenser enables the reset signal when its input signal, correlated with the voltage of the condenser, falls below a seond threshold. For enabling of the reset signal to be dependent on both the duration of the reduction in the input signal below the first threshold, as measured by the voltage present at the terminals of the condenser, as well as on the amount of reduction, the input signal of the second comparator consists of a linear combination of the input signal and the voltage of the condenser, effected by an adding element.

公开(公告)号：US5179300A

公开(公告)日：1993-01-12

申请号：US691768

申请日：1991-04-26

Applicant: Paolo Rolandi ,  Marco Dallabora ,  Marco Maccalli

Inventor： Paolo Rolandi ,  Marco Dallabora ,  Marco Maccalli

IPC: H03K19/0185 ,  H03K19/003 ,  H03K19/0175

CPC classification number: H03K19/00361

Abstract: A data output stage of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors associated to drive an output node of said stage, comprises first and second feedback loops which are structurally independent and respectively connected between said node and a corresponding gate electrode of each transistor to precharge said output node at a predetermined value and reduce the noise to ground during the switching phase.

公开(公告)号：US5165590A

公开(公告)日：1992-11-24

申请号：US867646

申请日：1992-04-13

Applicant: Carlo Cini ,  Angelo Massironi ,  Luigi Sisti

Inventor： Carlo Cini ,  Angelo Massironi ,  Luigi Sisti

IPC: H01L21/60 ,  H01L21/607 ,  H01L23/49 ,  H01L23/495

CPC classification number: H01L24/85 ,  H01L23/49541 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48799 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49505 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755

Abstract: A process for manufacturing devices with improved connections between the pins and the semiconductor material chip which integrates electronic components. In order to allow the integration of signal components and power components in a same device with a reduced use of area for the soldering pads and with high reliability of the connections, the connecting wires are made of different materials. Advantageously, the wires for the power connections are based on aluminum and have large diameters, and the wires for the signal connections are gold-based and have a small diameter. In order to ensure good soldering, the ends of the pins on which the connecting wires are to be soldered are gold-plated.

Abstract translation: 一种用于制造具有改进的引脚与半导体材料芯片之间的连接的器件的工艺，其集成了电子部件。 为了允许将信号部件和功率部件集成在相同的器件中，减少了对焊盘的使用面积，并具有高可靠性的连接，连接线由不同的材料制成。 有利地，用于电力连接的电线基于铝并且具有大的直径，并且用于信号连接的电线是金基的并且具有小的直径。 为了确保焊接良好，要焊接连接线的销的端部镀金。

公开(公告)号：US5160986A

公开(公告)日：1992-11-03

申请号：US759203

申请日：1991-09-11

Applicant: Orio Bellezza

Inventor： Orio Bellezza

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The matrix of EPROM memory cells comprises on a semiconductor substrate lines of source and drain parallel and alternated one to another, floating gate areas interposed in a checkerboard pattern between said source and drain lines and control gate lines parallel to one another and perpendicular to said source and drain lines in a superimposed condition with intermediate dielectric and aligned with respect to said floating gate areas. Field oxide areas are provided for, formed on the substrate between one and the other of said control gate lines and side fins of the floating gate areas and of the control gate lines superimposed over said field oxide areas.

Abstract translation: EPROM存储单元的矩阵包括在源极和漏极平行并交替的半导体衬底上，彼此交替布置在所述源极和漏极线之间的棋盘图案中的浮动栅极区域和彼此平行并垂直于所述源极的控制栅极线 以及具有中间电介质并且相对于所述浮动栅区对准的叠加状态的漏极线。 提供场氧化物区域，用于形成在衬底上的所述控制栅极线和浮栅区域的侧鳍之间以及叠加在所述场氧化物区域上的控制栅极线的侧鳍之间。

公开(公告)号：US5152168A

公开(公告)日：1992-10-06

申请号：US631018

申请日：1990-12-21

Applicant: Gabriele Barlocchi ,  Fabrizio Ghironi

Inventor： Gabriele Barlocchi ,  Fabrizio Ghironi

IPC: G01B7/28 ,  H01L21/66 ,  H01L21/68

CPC classification number: H01L21/681 ,  G01B7/28 ,  H01L22/12

Abstract: A method for the quantitative assessment of the degree of geometrical deformation undergone by a surface profile of a wafer following the formation of a conformal surface layer employs a simple mechanical profilometer, whose stylus is run over a target morphological detail comprising at least two mutually parallel ridges or reliefs which rise above the plane of the surface of the wafer for a height of between 0.1 and 0.5 .mu.m, and which enclose between them a depression of a width of between 2 and 4 .mu.m, in order to determine the elevation of the bottom of the valley between the two ridges relative to the plane of the surface of the wafer from which the ridges rise following the formation of one or more similar surface layers. The vertical measurement of the elevation undergone by the bottom of the valley in itself represents a quantitative index of the vertical and horizontal geometrical deformation undergone by the details of the surface profile of the wafer. In order to determine characteristics of automatic alignability by a particular apparatus employing said target details for automatic alignment, it is possible to establish a maximum value for said distortion index, determined as above, above which the automatic alignment capability is lost.

公开(公告)号：US5144172A

公开(公告)日：1992-09-01

申请号：US605271

申请日：1990-10-30

Applicant: Sergio Palara ,  Donato Tagliavia

Inventor： Sergio Palara ,  Donato Tagliavia

IPC: G01R31/02 ,  G01R19/165 ,  G01R31/26 ,  G05F3/22

CPC classification number: G05F3/22 ,  G01R31/2621

Abstract: A circuit for detecting the current in an MOS type power transistor comprises a detection transistor (T2) connected with its drain and gate in common to the power transistor (T1) and having characteristics such that the current flowing through it is equal to a fraction of the current (I1) flowing through the power transistor (T1). Downstream from the detection transistor (T2) is a comparison transistor (T6, T13) for comparing a first current (I3), which is equal to a fraction of the current flowing through the detection transistor, with a second or reference current (Ig1) having a pre-set value. The comparison transistor (T6, T13) produces a detection signal of the value of the current in the power transistor (I1) in relation to the difference between the first current (I3) and the reference current (Ig1).