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    Quantitative assessment of the geometrical distortion suffered by the profile of a semiconductor wafer
    1.
    发明授权
    Quantitative assessment of the geometrical distortion suffered by the profile of a semiconductor wafer 失效
    由半导体滤波器轮廓引起的几何失真的定量评估

    公开(公告)号：US5152168A

    公开(公告)日：1992-10-06

    申请号：US631018

    申请日：1990-12-21

    申请人： Gabriele Barlocchi ,  Fabrizio Ghironi

    发明人： Gabriele Barlocchi ,  Fabrizio Ghironi

    IPC分类号： G01B7/28 ,  H01L21/66 ,  H01L21/68

    CPC分类号： H01L21/681 ,  G01B7/28 ,  H01L22/12

    摘要： A method for the quantitative assessment of the degree of geometrical deformation undergone by a surface profile of a wafer following the formation of a conformal surface layer employs a simple mechanical profilometer, whose stylus is run over a target morphological detail comprising at least two mutually parallel ridges or reliefs which rise above the plane of the surface of the wafer for a height of between 0.1 and 0.5 .mu.m, and which enclose between them a depression of a width of between 2 and 4 .mu.m, in order to determine the elevation of the bottom of the valley between the two ridges relative to the plane of the surface of the wafer from which the ridges rise following the formation of one or more similar surface layers. The vertical measurement of the elevation undergone by the bottom of the valley in itself represents a quantitative index of the vertical and horizontal geometrical deformation undergone by the details of the surface profile of the wafer. In order to determine characteristics of automatic alignability by a particular apparatus employing said target details for automatic alignment, it is possible to establish a maximum value for said distortion index, determined as above, above which the automatic alignment capability is lost.

    Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured
    4.
    发明授权
    Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured 有权
    制造具有SOI绝缘阱和半导体晶片的半导体晶片的制造方法

    公开(公告)号：US07906406B2

    公开(公告)日：2011-03-15

    申请号：US11879738

    申请日：2007-07-17

    申请人： Gabriele Barlocchi ,  Pietro Corona ,  Flavio Francesco Villa

    发明人： Gabriele Barlocchi ,  Pietro Corona ,  Flavio Francesco Villa

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76264 ,  H01L21/7682

    摘要： A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.

    摘要翻译： 制造包括SOI绝缘阱的半导体晶片的工艺包括在半导体主体的管芯区域中形成穿过掩埋腔并分布在管芯区域中的掩埋腔和半导体结构元件。 该方法还包括选择性地将第一相邻的半导体结构元件氧化并设置在封闭区域内的步骤，并且防止第二半导体结构元件在封闭区域外的氧化，从而在闭合区域内选择性地形成管芯埋入介电层。

    PROCESS FOR MANUFACTURING A MEMBRANE OF SEMICONDUCTOR MATERIAL INTEGRATED IN, AND ELECTRICALLY INSULATED FROM, A SUBSTRATE
    6.
    发明申请
    PROCESS FOR MANUFACTURING A MEMBRANE OF SEMICONDUCTOR MATERIAL INTEGRATED IN, AND ELECTRICALLY INSULATED FROM, A SUBSTRATE 有权
    一种制造半导体材料膜的方法，集成在一个基板上并电绝缘

    公开(公告)号：US20080224242A1

    公开(公告)日：2008-09-18

    申请号：US12047830

    申请日：2008-03-13

    申请人： Flavio Franceso Villa ,  Pietro Corona ,  Chantal Combi ,  Lorenzo Baldo ,  Gabriele Barlocchi

    发明人： Flavio Franceso Villa ,  Pietro Corona ,  Chantal Combi ,  Lorenzo Baldo ,  Gabriele Barlocchi

    IPC分类号： H01L29/96 ,  H01L21/02

    CPC分类号： B81C1/00158

    摘要： A process for manufacturing an integrated membrane made of semiconductor material includes the step of forming, in a monolithic body of semiconductor material having a front face, a buried cavity, extending at a distance from the front face and delimiting with the front face a surface region of the monolithic body, the surface region forming a membrane that is suspended above the buried cavity. The process further envisages the step of forming an insulation structure in a surface portion of the monolithic body to electrically insulate the membrane from the monolithic body; and the further and distinct step of setting the insulation structure at a distance from the membrane so that it will be positioned outside the membrane at a non-zero distance of separation.

    摘要翻译： 制造由半导体材料制成的集成膜的方法包括以下步骤：在具有前表面的半导体材料的整体中形成一个与前表面相距一定距离的掩埋腔， 的单体，表面区域形成悬浮在掩埋腔上方的膜。 该方法进一步设想在整体式主体的表面部分形成绝缘结构以将膜与整体式电绝缘的步骤; 以及将绝缘结构设置在离膜一定距离处的进一步和不同的步骤，使得其将以非零分离距离定位在膜的外部。

    Process for manufacturing thick suspended structures of semiconductor material
    8.
    发明申请
    Process for manufacturing thick suspended structures of semiconductor material 有权
    用于制造半导体材料的厚悬浮结构的方法

    公开(公告)号：US20070126071A1

    公开(公告)日：2007-06-07

    申请号：US11541376

    申请日：2006-09-27

    申请人： Pietro Corona ,  Flavio Villa ,  Gabriele Barlocchi

    发明人： Pietro Corona ,  Flavio Villa ,  Gabriele Barlocchi

    IPC分类号： H01L29/84 ,  H01L21/00

    CPC分类号： B81C1/00158 ,  B81B2201/025 ,  B81B2203/0109 ,  B81B2203/0315

    摘要： A process for manufacturing a suspended structure of semiconductor material envisages the steps of: providing a monolithic body of semiconductor material having a front face; forming a buried cavity within the monolithic body, extending at a distance from the front face and delimiting, with the front face, a surface region of the monolithic body, said surface region having a first thickness; carrying out a thickening thermal treatment such as to cause a migration of semiconductor material of the monolithic body towards the surface region and thus form a suspended structure above the buried cavity, the suspended structure having a second thickness greater than the first thickness. The thickening thermal treatment is an annealing treatment.

    摘要翻译： 制造半导体材料的悬浮结构的方法设想的步骤：提供具有正面的半导体材料的整体; 在所述整体式主体内形成掩埋空腔，所述掩埋腔在所述前表面的一定距离处延伸并且与所述前表面一起界定所述整体式主体的表面区域，所述表面区域具有第一厚度; 进行增稠热处理，使得整体式体的半导体材料朝向表面区域移动，从而在掩埋空腔之上形成悬浮结构，该悬浮结构的第二厚度大于第一厚度。 增稠热处理是退火处理。

    Integrated differential pressure sensor and manufacturing process thereof
    9.
    发明申请
    Integrated differential pressure sensor and manufacturing process thereof 有权
    集成差压传感器及其制造工艺

    公开(公告)号：US20060260408A1

    公开(公告)日：2006-11-23

    申请号：US11417683

    申请日：2006-05-04

    申请人： Flavio Villa ,  Pietro Corona ,  Gabriele Barlocchi ,  Lorenzo Baldo

    发明人： Flavio Villa ,  Pietro Corona ,  Gabriele Barlocchi ,  Lorenzo Baldo

    IPC分类号： B05D5/12 ,  G01L7/08

    CPC分类号： G01L9/0045 ,  G01L13/025

    摘要： A process for manufacturing an integrated differential pressure sensor includes forming, in a monolithic body of semiconductor material having a first face and a second face, a cavity extending at a distance from the first face and delimiting therewith a flexible membrane, forming an access passage in fluid communication with the cavity, and forming, in the flexible membrane, at least one transduction element configured so as to convert a deformation of the flexible membrane into electrical signals. The cavity is formed in a position set at a distance from the second face and delimits, together with the second face, a portion of the monolithic body. In order to form the access passage, the monolithic body is etched so as to form an access trench extending through it.

    摘要翻译： 一种用于制造集成差压传感器的方法，包括在具有第一面和第二面的半导体材料的整体中形成一个与第一面相距一定距离的空腔，并将其限定在柔性膜上，形成入口通道 与空腔流体连通，以及在柔性膜中形成至少一个换能元件，其构造成将柔性膜的变形转换为电信号。 空腔形成在距第二面一定距离处的位置，并与第二面一起界定整体式的一部分。 为了形成进入通道，对整体式主体进行蚀刻以便形成延伸通过其的通道沟槽。

    Integrated chemical microreactor with separated channels
    10.
    发明申请
    Integrated chemical microreactor with separated channels 有权
    具有分离通道的集成化学微反应器

    公开(公告)号：US20050142597A1

    公开(公告)日：2005-06-30

    申请号：US10997235

    申请日：2004-11-24

    申请人： Ubaldo Mastromatteo ,  Flavio Villa ,  Gabriele Barlocchi

    发明人： Ubaldo Mastromatteo ,  Flavio Villa ,  Gabriele Barlocchi

    IPC分类号： B01L3/00 ,  B01L7/00 ,  B81B3/00 ,  C12M1/34 ,  C12Q1/68 ,  H01L21/00

    CPC分类号： B01L3/502715 ,  B01L3/5025 ,  B01L3/502707 ,  B01L7/52 ,  B01L2200/027 ,  B01L2200/12 ,  B01L2300/044 ,  B01L2300/0816 ,  B01L2300/1827

    摘要： The microreactor is formed by a sandwich including a first body, an intermediate sealing layer and a second body. A buried channel extends in the first body and communicates with the surface of the first body through a first and a second apertures. A first and a second reservoirs are formed in the second body and are at least partially aligned with the first and second apertures. The sealing layer separates the first aperture from the first reservoir and the second aperture from the second reservoir, thereby avoiding contamination of liquids contained in the buried channel from the outside and from any adjacent buried channels. The sealing layer is perforated during use of the device, but a resilient plug can be used to reseal the device.

    摘要翻译： 微反应器由包括第一主体，中间密封层和第二主体的夹层形成。 掩埋通道在第一主体中延伸并且通过第一和第二孔与第一主体的表面连通。 第一和第二储存器形成在第二主体中并且至少部分地与第一和第二孔对准。 密封层将第一孔与第一储存器和第二孔分隔开来自第二储存器，从而避免了从外部和任何相邻的埋入通道污染包含在掩埋通道中的液体。 在使用该装置期间密封层是穿孔的，但是可以使用弹性塞来重新密封装置。