公开(公告)号：US12153524B2

公开(公告)日：2024-11-26

申请号：US17957358

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Marko Scrbak ,  Gabriel H. Loh ,  Akhil Arunkumar

IPC: G06F12/0862

Abstract: A disclosed computing device includes at least one prefetcher and a processing device communicatively coupled to the prefetcher. The processing device is configured to detect a throttling instruction that indicates a start of a throttling region. The computing device is further configured to prevent the prefetcher from being trained on one or more memory instructions included in the throttling region in response to the throttling instruction. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US12141915B2

公开(公告)日：2024-11-12

申请号：US17028811

申请日：2020-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Christopher J. Brennan ,  Fataneh F. Ghodrat ,  Tien E. Wei

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/50

Abstract: Techniques for performing multi-sample anti-aliasing operations are provided. The techniques include detecting an instruction for a multi-sample anti-aliasing load operation; determining a sampling rate of source data for the load operation, data storage format of the source data, and loading mode indicating whether the load operation requests same or different color components, or depth data; and based on the determined sampling rate, data storage format, and loading mode, load data from a multi-sample source into a register.

公开(公告)号：US12141038B2

公开(公告)日：2024-11-12

申请号：US18084350

申请日：2022-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F11/14 ,  G06F3/06

Abstract: A memory controller includes a command queue, a memory interface queue, at least one storage queue, and a replay control circuit. The command queue has a first input for receiving memory access commands. The memory interface queue receives commands selected from the command queue and couples to a heterogeneous memory channel which is coupled to at least one non-volatile storage class memory (SCM) module. The at least one storage queue stores memory access commands that are placed in the memory interface queue. The replay control circuit detects that an error has occurred requiring a recovery sequence, and in response to the error, initiates the recovery sequence. In the recovery sequence, the replay control circuit transmits selected memory access commands from the at least one storage queue by grouping non-volatile read commands together separately from all pending volatile reads, volatile writes, and non-volatile writes.

公开(公告)号：US12135653B2

公开(公告)日：2024-11-05

申请号：US18158212

申请日：2023-01-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander D. Breslow ,  John Kalamatianos

IPC: G06F12/0895 ,  H03M7/30

Abstract: Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the cache line. This dictionary is then selected to compress the cache line. An offset is added to the base index of the cache line to generate a full index in order to map the cache line to the set corresponding to this chosen dictionary. The compressed cache line is stored in this set with the chosen dictionary, and the offset is stored in the corresponding tag array entry.

公开(公告)号：US12135625B2

公开(公告)日：2024-11-05

申请号：US18089135

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Vilas Sridharan ,  Hanbing Liu ,  Francisco L. Duran

IPC: G06F11/26 ,  G06F11/07

Abstract: An exemplary system includes and/or represents an agent and a machine check architecture. In one example, the machine check architecture includes and/or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture also includes and/or represents at least one error-injection register configured to cause the circuit to inject at least one fabricated error report into the reporting register in response to a write operation performed by the agent on at least one bit of the error-injection register. Various other devices, systems, and methods are also disclosed.

公开(公告)号：US12131063B2

公开(公告)日：2024-10-29

申请号：US17219138

申请日：2021-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Lepak

IPC: G06F3/00 ,  G06F3/06 ,  G06F12/0882 ,  G06F12/1009

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0679 ,  G06F12/0882 ,  G06F12/1009

Abstract: Methods and apparatus offload tiered memories management. The method includes obtaining a pointer to a stored memory management structure associated with tiered memories, where the memory management structure includes a plurality of memory management entries and each memory management entry of the plurality of memory management entries includes information for a memory section in one of the tiered memories. In some instances, the method includes scanning at least a part of the plurality of memory management entries. In certain instances, the method includes generating a memory profile list, where the memory profile list includes a plurality of profile entries and each profile entry of the plurality of profile entries corresponding to a scanned memory management entry in the memory management structure.

公开(公告)号：US12130741B2

公开(公告)日：2024-10-29

申请号：US18058534

申请日：2022-11-23

Applicant: Advanced Micro Devices, Inc.

Inventor： SeyedMohammad SeyedzadehDelcheh ,  Shomit N. Das ,  Bradford Michael Beckmann

IPC: G06F12/02 ,  G06F11/30 ,  G06F12/0871 ,  G06F12/0897

CPC classification number: G06F12/0871 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/0897 ,  G06F2212/401

Abstract: Systems, apparatuses, and methods for implementing a multi-tiered approach to cache compression are disclosed. A cache includes a cache controller, light compressor, and heavy compressor. The decision on which compressor to use for compressing cache lines is made based on certain resource availability such as cache capacity or memory bandwidth. This allows the cache to opportunistically use complex algorithms for compression while limiting the adverse effects of high decompression latency on system performance. To address the above issue, the proposed design takes advantage of the heavy compressors for effectively reducing memory bandwidth in high bandwidth memory (HBM) interfaces as long as they do not sacrifice system performance. Accordingly, the cache combines light and heavy compressors with a decision-making unit to achieve reduced off-chip memory traffic without sacrificing system performance.

公开(公告)号：US12130692B2

公开(公告)日：2024-10-29

申请号：US17993562

申请日：2022-11-23

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Karthik Rao ,  Indrani Paul ,  Donny Yi ,  Oleksandr Khodorkovsky ,  Leonardo De Paula Rosa Piga ,  Wonje Choi ,  Dana G. Lewis ,  Sriram Sambamurthy

IPC: G06F1/32 ,  G06F1/3287

CPC classification number: G06F1/3287

Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.

公开(公告)号：US12130690B2

公开(公告)日：2024-10-29

申请号：US18316865

申请日：2023-05-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Alexander J. Branover ,  Christopher T. Weaver ,  Benjamin Tsien ,  Indrani Paul ,  Mihir Shaileshbhai Doctor ,  Thomas J. Gibney ,  John P. Petry ,  Dennis Au ,  Oswin Hall

IPC: G06F1/32 ,  G06F1/3209 ,  G06F1/3234

CPC classification number: G06F1/3265 ,  G06F1/3209 ,  G06F1/3275

Abstract: A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.

公开(公告)号：US20240354221A1

公开(公告)日：2024-10-24

申请号：US18760329

申请日：2024-07-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Max Alt ,  Paulo Roberto Pereira de Souza filho

IPC: G06F11/36 ,  G06F8/41 ,  G06F16/23 ,  G06F16/245

CPC classification number: G06F11/3612 ,  G06F8/443 ,  G06F16/2379 ,  G06F16/245

Abstract: Systems and methods for building applications by automatically incorporating application performance data into the application build process are disclosed. By capturing build settings and performance data from prior applications being executed on different computing systems such as bare metal and virtualized cloud instances, a performance database may be maintained and used to predict build settings that improve application performance (e.g., on a specific computing system or computing system configuration).