公开(公告)号：US20060067128A1

公开(公告)日：2006-03-30

申请号：US11217920

申请日：2005-09-01

申请人： Andrei Mihnea ,  Chun Chen

发明人： Andrei Mihnea ,  Chun Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C16/08 ,  G11C16/14 ,  H01L27/115

摘要： Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

公开(公告)号：US20060007747A1

公开(公告)日：2006-01-12

申请号：US11217820

申请日：2005-09-01

申请人： Andrei Mihnea ,  Chun Chen

发明人： Andrei Mihnea ,  Chun Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/08 ,  G11C16/14 ,  H01L27/115

摘要： Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

公开(公告)号：US20060002167A1

公开(公告)日：2006-01-05

申请号：US10881951

申请日：2004-06-30

申请人： Paul Rudeck ,  Andrei Mihnea ,  Andrew Bicksler

发明人： Paul Rudeck ,  Andrei Mihnea ,  Andrew Bicksler

IPC分类号： G11C17/00

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427

摘要： A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.

公开(公告)号：US06563741B2

公开(公告)日：2003-05-13

申请号：US09772667

申请日：2001-01-30

申请人： Andrei Mihnea ,  Chun Chen ,  Paul Rudeck ,  Andrew R. Bicksler

发明人： Andrei Mihnea ,  Chun Chen ,  Paul Rudeck ,  Andrew R. Bicksler

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3404

摘要： A non-volatile memory device includes an improved method for erasing a block of stack-gate single transistor flash memory cells. The memory performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array. The erase pulse(s) fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block. The block convergence operation brings a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunnelling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential. The memory can implement several biasing schemes while performing the block convergence operation.

公开(公告)号：US06426898B1

公开(公告)日：2002-07-30

申请号：US09797682

申请日：2001-03-05

申请人： Andrei Mihnea ,  Jeffrey Kessenich ,  Chun Chen

发明人： Andrei Mihnea ,  Jeffrey Kessenich ,  Chun Chen

IPC分类号： G11C700

CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445

摘要： A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.

摘要翻译： 公开了一种擦除闪存器件中的存储单元的方法，该闪速存储器件将通过隧道氧化物的电子重新捕获隧道氧化物中的空穴（在擦除操作之后）。 该方法使用擦除操作，擦除所有进行擦除操作的存储单元。 对过度消耗的细胞进行细胞愈合操作。 愈合操作使电子通过隧道氧化物并与被捕获的孔重组。 该复合基本上减少了隧道氧化物内的被捕获的孔，而不降低擦除操作的速度。 此外，通过减少捕获的空穴，闪存单元的电荷保持率，总体性能和耐久性显着增加。

公开(公告)号：US5793079A

公开(公告)日：1998-08-11

申请号：US681444

申请日：1996-07-22

申请人： Sorin Georgescu ,  Andrei Mihnea ,  Radu Vanco

发明人： Sorin Georgescu ,  Andrei Mihnea ,  Radu Vanco

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01K27/788

CPC分类号： H01L27/115 ,  G11C16/0491

摘要： An electrically alterable semiconductor memory device having an array of memory cells formed by individual transistors. The structure of the memory cells is compact and facilitates high density memory devices and is particularly well suited for contactless, virtual ground arrays. The memory cells can be read and programmed a page at a time. The memory cells can also be programmed using source-side hot-electron injection with improved efficiency and lowered programming currents. In one embodiment, the structure of the memory cells include: a substrate having a diffused source region, a diffused drain region, and a channel region between the diffused source region and the diffused drain region; a select gate positioned adjacent to the channel region, the select gate being positioned over a first portion of the channel region, the first portion being adjacent to the diffused source region and extending therefrom towards the diffused drain region; a floating gate adjacent to the channel region, the floating gate being positioned over a second portion of the channel region, the second portion being adjacent to the diffused drain region and extending therefrom towards the diffused source region; and a control gate over the floating gate. By providing select gates in the memory cells, problematic reverse currents in adjacent unselected memory cells of a contactless, virtual ground array are blocked or prevented during programming. The invention also pertains to a method for fabricating the semiconductor memory device.

摘要翻译： 具有由单个晶体管形成的存储单元阵列的电可变半导体存储器件。 存储单元的结构紧凑，便于高密度存储器件，特别适用于非接触式虚拟接地阵列。 可以一次读取和编程一个页面的存储单元。 存储单元也可以使用源侧热电子注入进行编程，提高效率和降低编程电流。 在一个实施例中，存储单元的结构包括：具有扩散源极区域，扩散漏极区域和扩散源极区域与扩散漏极区域之间的沟道区域的衬底; 所述选择栅极定位在所述沟道区附近，所述选择栅极位于所述沟道区的第一部分之上，所述第一部分与所述扩散源极区相邻并从其延伸到所述扩散的漏极区; 与沟道区相邻的浮置栅极，浮置栅极定位在沟道区的第二部分上方，第二部分与扩散漏极区相邻并从其延伸到扩散源极区; 以及在浮动门上的控制门。 通过在存储器单元中提供选择栅极，在编程期间阻塞或防止非接触式虚拟接地阵列的相邻未选择的存储单元中的有问题的反向电流。 本发明还涉及一种用于制造半导体存储器件的方法。

公开(公告)号：US08389971B2

公开(公告)日：2013-03-05

申请号：US12905047

申请日：2010-10-14

申请人： Yung-Tin Chen ,  Chuanbin Pan ,  Andrei Mihnea ,  Steven Maxwell ,  Kun Hou

发明人： Yung-Tin Chen ,  Chuanbin Pan ,  Andrei Mihnea ,  Steven Maxwell ,  Kun Hou

IPC分类号： H01L47/00

CPC分类号： H01L45/146 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1616 ,  Y10S438/957

摘要： In some embodiments, a memory cell is provided that includes a storage element formed from an MIM stack including (1) a first conductive layer; (2) an RRS layer formed above the first conductive layer; and (3) a second conductive layer formed above the RRS layer, at least one of the first and second conductive layers comprising a first semiconductor material layer. The memory cell includes a steering element coupled to the storage element, the steering element formed from the first semiconductor material layer of the MIM stack and one or more additional material layers. Numerous other aspects are provided.

摘要翻译： 在一些实施例中，提供了一种存储单元，其包括由MIM堆叠形成的存储元件，所述存储元件包括：（1）第一导电层; （2）形成在第一导电层上方的RRS层; 和（3）形成在RRS层之上的第二导电层，第一和第二导电层中的至少一个包括第一半导体材料层。 存储单元包括耦合到存储元件的操纵元件，由MIM堆叠的第一半导体材料层形成的操纵元件和一个或多个附加材料层。 提供了许多其他方面。

公开(公告)号：US08274130B2

公开(公告)日：2012-09-25

申请号：US12582509

申请日：2009-10-20

申请人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

发明人： Andrei Mihnea ,  Deepak C. Sekar ,  George Samachisa ,  Roy Scheuerlein ,  Li Xiao

IPC分类号： H01L29/861

CPC分类号： G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/24

摘要： A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P−/N+ device or a P+/N−/P+ device.

摘要翻译： 描述了一种用于形成使用穿通二极管作为与可逆电阻率切换元件串联的转向元件的存储系统的存储系统和方法。 穿通二极管允许交叉点存储器阵列的双极性操作。 穿通二极管可具有对称的非线性电流/电压关系。 穿通二极管在选择的电池的高偏压下具有高电流，对于未选择的电池，在低偏压下具有低泄漏电流。 因此，它与具有电阻式开关元件的交叉点存储器阵列中的双极开关兼容。 穿通二极管可以是N + / P- / N +器件或P + / N- / P +器件。

公开(公告)号：US08264885B2

公开(公告)日：2012-09-11

申请号：US13082965

申请日：2011-04-08

申请人： Akira Goda ,  Andrei Mihnea

发明人： Akira Goda ,  Andrei Mihnea

IPC分类号： G11C16/16

CPC分类号： G11C16/06 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5634

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.

摘要翻译： 本公开的实施例提供用于操作存储器单元的方法，设备，模块和系统。 一种方法包括：对所选择的一组存储器单元执行擦除操作，所选择的组包括多个参考单元和多个数据单元; 对作为擦除操作的一部分的参考单元的数量进行编程监视操作; 以及至少部分地基于对参考单元的数量执行的编程监视操作来确定与操作所述数据单元的数量相关联的特定操作参数的数量。

公开(公告)号：US20120176831A1

公开(公告)日：2012-07-12

申请号：US13424131

申请日：2012-03-19

申请人： Li Xiao ,  Chandu Gorla ,  Abhijit Bandyopadhyay ,  Andrei Mihnea

发明人： Li Xiao ,  Chandu Gorla ,  Abhijit Bandyopadhyay ,  Andrei Mihnea

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： G11C13/0007 ,  G11C5/02 ,  G11C8/10 ,  G11C13/0023 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

摘要： A memory cell in a 3-D read and write memory device has two bipolar resistance-switching layers with different respective switching currents. A low current resistance-switching layer can be switched in set and reset processes while a high current resistance-switching layer remains in a reset state and acts as a protection resistor to prevent excessively high currents on the low current resistance-switching layer. The low and high current resistance-switching layers can be of the same material such as a metal oxide, where the layers differ in terms of thickness, doping, leakiness, metal richness or other variables. Or, the low and high current resistance-switching layers can be of different materials, having one or more layers each. The high current resistance-switching layer can have a switching current which is greater than a switching current of the low current resistance-switching layer by a factor of at least 1.5 or 2.0, for instance.

摘要翻译： 3-D读写存储器件中的存储单元具有两个具有不同开关电流的双极性电阻切换层。 低电流电阻切换层可以在置位和复位过程中被切换，而高电流电阻切换层保持复位状态，并且作为保护电阻来防止低电流电阻切换层上的过大电流。 低电流和高电流电阻切换层可以是相同的材料，例如金属氧化物，其中层的厚度，掺杂，泄漏，金属浓度等变化不同。 或者，低电流和高电流电阻切换层可以是不同的材料，每个具有一个或多个层。 高电流电阻切换层例如可以具有比低电流电阻切换层的开关电流大至少1.5或2.0的开关电流。