公开(公告)号：US06867096B2

公开(公告)日：2005-03-15

申请号：US10855165

申请日：2004-05-27

Applicant: Sung-IL Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

Inventor： Sung-IL Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/3213

CPC classification number: H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract translation: 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层 电极在下电极上。

公开(公告)号：US07842450B2

公开(公告)日：2010-11-30

申请号：US11711781

申请日：2007-02-28

Applicant: Doo-youl Lee ,  Suk-joo Lee ,  Yool Kang ,  Han-ku Cho ,  Chang-jin Kang ,  Jae-ok Yoo ,  Sung-chan Park

Inventor： Doo-youl Lee ,  Suk-joo Lee ,  Yool Kang ,  Han-ku Cho ,  Chang-jin Kang ,  Jae-ok Yoo ,  Sung-chan Park

IPC: G03F7/00

CPC classification number: H01L21/0337

Abstract: A method of forming a semiconductor device includes forming a first mask pattern on a target layer, the first mask pattern exposing a first portion of the target layer, forming an intermediate material layer, including depositing an intermediate material layer film on a side of the first mask pattern and the first portion of the target layer, and thinning the intermediate material layer film to form the intermediate material layer, forming a second mask pattern that exposes a second portion of the intermediate material layer, removing the exposed second portion of the intermediate material layer to expose the target layer, and patterning the target layer using the first and second mask patterns as patterning masks.

Abstract translation: 形成半导体器件的方法包括：在目标层上形成第一掩模图案，第一掩模图案暴露目标层的第一部分，形成中间材料层，包括在第一掩模图案的一侧上沉积中间材料层膜 掩模图案和目标层的第一部分，并且使中间材料层膜变薄以形成中间材料层，形成暴露中间材料层的第二部分的第二掩模图案，去除中间材料的暴露的第二部分 层以露出目标层，以及使用第一和第二掩模图案作为图案掩模来图案化目标层。

公开(公告)号：US07402488B2

公开(公告)日：2008-07-22

申请号：US11159130

申请日：2005-06-23

Applicant: Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

Inventor： Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

IPC: H01L21/8242

CPC classification number: H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L27/10852 ,  H01L28/91

Abstract: A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.

Abstract translation: 半导体存储器件的制造方法包括在半导体衬底上形成含碳层，在含碳层上形成绝缘层图案，将含碳层的上表面部分地露出的绝缘层图案， 蚀刻含碳层的暴露部分，形成用于限定存储节点孔的含碳层图案，在存储节点孔内部形成底部电极，在存储节点孔内部的底部电极上形成电介质层， 所述介电层覆盖所述底部电极，并且在所述存储节点孔内部的所述电介质层上形成上部电极，所述上部电极覆盖所述电介质层。

公开(公告)号：US20080087931A1

公开(公告)日：2008-04-17

申请号：US11869400

申请日：2007-10-09

Applicant: Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

Inventor： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC: H01L27/108 ,  H01L21/3205 ,  H01L21/8242

CPC classification number: H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract translation: 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层， 选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

公开(公告)号：US20080085601A1

公开(公告)日：2008-04-10

申请号：US11590663

申请日：2006-10-31

Applicant: Sung-Chan Park ,  Chang-Jin Kang

Inventor： Sung-Chan Park ,  Chang-Jin Kang

IPC: B05D5/12 ,  H01L21/4763 ,  H05K3/00

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

Abstract: A method of forming a contact hole includes forming a plurality of lower patterns on a substrate. An insulation layer is formed on the lower patterns. A self-assemble induction layer is formed on the insulation layer. A recess is formed in the self-assemble induction layer in alignment with the lower patterns. A block copolymer layer is formed in the recess to form a polymer domain at a distance from a sidewall of the recess and a polymer matrix surrounding the polymer domain. The polymer domain is removed. The self-assemble induction layer is etched using the polymer matrix as a mask to form an opening through the self-assemble induction layer to expose the insulation layer. The insulation layer exposed by the opening is etched using the self-assemble induction layer as a mask so as to form a contact hole.

Abstract translation: 形成接触孔的方法包括在基板上形成多个下部图案。 在下部图案上形成绝缘层。 在绝缘层上形成自组装感应层。 在自组装感应层中形成与下部图形对准的凹部。 在凹部中形成嵌段共聚物层，以形成与凹陷的侧壁相距一定距离的聚合物结构域和围绕聚合物结构域的聚合物基体。 去除聚合物结构域。 使用聚合物基质作为掩模蚀刻自组装感应层，以通过自组装感应层形成开口以暴露绝缘层。 使用自组装感应层作为掩模蚀刻由开口暴露的绝缘层，以形成接触孔。

公开(公告)号：US20080081432A1

公开(公告)日：2008-04-03

申请号：US11624905

申请日：2007-01-19

Applicant: Yong-Jin KIM ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

Inventor： Yong-Jin KIM ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC: H01L21/76

CPC classification number: H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner wails of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

Abstract translation: 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US07338849B2

公开(公告)日：2008-03-04

申请号：US11261820

申请日：2005-10-28

Applicant: Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

Inventor： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC: H01L21/8238 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.

Abstract translation: 提供了制造闪速存储器件的方法和由此制造的闪存器件。 一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。 在有源区上形成多个第一导电层图案。 第一导电层图案在活性区域的长度方向上彼此间隔开。 在半导体衬底和第一导电层图案上共形形成绝缘层。 在绝缘层上形成第二导电层。 图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。 第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

公开(公告)号：US07303957B2

公开(公告)日：2007-12-04

申请号：US11517254

申请日：2006-09-08

Applicant: Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Jai-hyuk Song

Inventor： Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Jai-hyuk Song

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method of fabricating a flash memory device using a process for forming a self-aligned floating gate is provided. The method comprises forming mask patterns on a substrate, etching the substrate using the mask patterns as an etch mask to form a plurality of trenches, and filling the trenches with a first insulating layer, wherein sidewalls of the mask patterns remain exposed after filling the trenches with the first insulating layer. The method further comprises forming spacers on the exposed sidewalls of the mask patterns, filling upper insulating spaces with a second insulating layer thereby defining isolation layers, and removing the mask patterns and the spacers.

公开(公告)号：US20070059876A1

公开(公告)日：2007-03-15

申请号：US11517254

申请日：2006-09-08

Applicant: Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Jai-hyuk Song

Inventor： Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Jai-hyuk Song

IPC: H01L21/8238

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method of fabricating a flash memory device using a process for forming a self-aligned floating gate is provided. The method comprises forming mask patterns on a substrate, etching the substrate using the mask patterns as an etch mask to form a plurality of trenches, and filling the trenches with a first insulating layer, wherein sidewalls of the mask patterns remain exposed after filling the trenches with the first insulating layer. The method further comprises forming spacers on the exposed sidewalls of the mask patterns, filling upper insulating spaces with a second insulating layer thereby defining isolation layers, and removing the mask patterns and the spacers.

Abstract translation: 提供了一种使用用于形成自对准浮动栅极的工艺来制造闪速存储器件的方法。 该方法包括在衬底上形成掩模图案，使用掩模图案蚀刻衬底作为蚀刻掩模以形成多个沟槽，并用第一绝缘层填充沟槽，其中掩模图案的侧壁在填充沟槽之后保持暴露 与第一绝缘层。 该方法还包括在掩模图案的暴露的侧壁上形成间隔物，用第二绝缘层填充上绝缘空间，从而限定隔离层，以及去除掩模图案和间隔物。

公开(公告)号：US20070023916A1

公开(公告)日：2007-02-01

申请号：US11494469

申请日：2006-07-28

Applicant: Jung-hwan Hah ,  Yun-sook Chae ,  Han-ku Cho ,  Chang-jin Kang ,  Sang-gyun Woo ,  Man-hyoung Ryoo ,  Young-jae Jung

Inventor： Jung-hwan Hah ,  Yun-sook Chae ,  Han-ku Cho ,  Chang-jin Kang ,  Sang-gyun Woo ,  Man-hyoung Ryoo ,  Young-jae Jung

IPC: H01L23/52

CPC classification number: H01L21/31144 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/32139

Abstract: The semiconductor structure includes an etch target layer to be pattemed, a multiple bottom anti-reflective coating (BARC) layer, and a photoresist (PR) pattern. The multiple BARC layer includes a first mask layer formed on the etch target layer and containing carbon, and a second mask layer formed on the first mask layer and containing silicon. A PR layer formed on the multiple BARC layer undergoes photolithography to form the PR pattern on the multiple BARC layer. The multiple BARC layer has a reflectance of 2% or less, and an interface angle between the PR pattern and the multiple BARC layer is 80° to 90°.

Abstract translation: 该半导体结构包括要被图案化的蚀刻目标层，多个底部抗反射涂层（BARC）层和光致抗蚀剂（PR）图案。 多个BARC层包括形成在蚀刻靶层上并含有碳的第一掩模层和形成在第一掩模层上并含有硅的第二掩模层。 形成在多个BARC层上的PR层经历光刻以在多个BARC层上形成PR图案。 多个BARC层的反射率为2％以下，PR图案与多个BARC层之间的界面角为80°〜90°。