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    DRAM devices having an increased density layout
    5.
    发明授权
    DRAM devices having an increased density layout 失效
    具有增加的密度布局的DRAM器件

    公开(公告)号：US07221014B2

    公开(公告)日：2007-05-22

    申请号：US11015993

    申请日：2004-12-17

    申请人： Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

    发明人： Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

    IPC分类号： H01L29/74 ,  H01L29/76

    CPC分类号： H01L27/10888 ,  H01L27/0207 ,  H01L27/10814

    摘要： DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.

    摘要翻译： DRAM装置包括沿第一方向延伸的多个字线和沿第二方向延伸并与字线相交的多个位线。 提供了多个有源区域，其被电耦合到字线和位线。 每个有源区域以最小线宽度F来限定具有6F 2的面积的单个单元存储单元。每个有源区域可以仅由一条字线重叠，并且有源区域 可以由隔离区限定。

    Method of forming trench in semiconductor device
    6.
    发明申请
    Method of forming trench in semiconductor device 失效
    在半导体器件中形成沟槽的方法

    公开(公告)号：US20050266646A1

    公开(公告)日：2005-12-01

    申请号：US11080891

    申请日：2005-03-16

    申请人： Doo-hoon Goo ,  Si-hyeung Lee ,  Han-ku Cho ,  Sang-gyun Woo ,  Gi-sung Yeo

    发明人： Doo-hoon Goo ,  Si-hyeung Lee ,  Han-ku Cho ,  Sang-gyun Woo ,  Gi-sung Yeo

    IPC分类号： H01L21/76 ,  H01L21/00 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/02

    CPC分类号： H01L27/10876 ,  H01L21/3083 ,  H01L27/0207

    摘要： There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of a first active region in a lateral direction, and also across another second active region in parallel with the first active region in a diagonal direction, and the extension is cut not to reach an isolation region between two third active regions that are in parallel with the second active region in a diagonal direction, and have noses facing each other in a longitudinal direction, and the layout includes an alignment of a plurality of open regions, which are discontinuously aligned. An etch mask is formed using the layout, and a semiconductor substrate is etched using the etch mask, and a trench for a recessed channel is formed on the active region.

    摘要翻译： 提供了一种形成用于晶体管的凹槽的沟槽的方法及其布局。 根据本发明的一个方面的凹陷通道的布局被形成为使得开放区域跨越横向方向上的第一有源区域中的至少一个延伸，并且还跨越与第一活性物体平行的另一个第二有源区域 区域，并且延伸部被切割成不能在对角线方向上到达与第二有源区域平行的两个第三有源区域之间的隔离区域，并且在纵向方向上具有彼此面对的鼻子，并且布局 包括不连续对准的多个开放区域的对准。 使用布局形成蚀刻掩模，并且使用蚀刻掩模蚀刻半导体衬底，并且在有源区上形成用于凹陷沟道的沟槽。

    Double photolithography methods with reduced intermixing of solvents
    7.
    发明申请
    Double photolithography methods with reduced intermixing of solvents 审中-公开
    双光刻法减少了溶剂的混合

    公开(公告)号：US20060127816A1

    公开(公告)日：2006-06-15

    申请号：US11296816

    申请日：2005-12-07

    申请人： Yool Kang ,  Han-ku Cho ,  Sang-Gyun Woo ,  Suk-Joo Lee ,  Man-Hyung Ryoo ,  Mitsuhiro Hata ,  Hyung-Rae Lee

    发明人： Yool Kang ,  Han-ku Cho ,  Sang-Gyun Woo ,  Suk-Joo Lee ,  Man-Hyung Ryoo ,  Mitsuhiro Hata ,  Hyung-Rae Lee

    IPC分类号： G03F7/00

    CPC分类号： G03F7/0035 ,  G03F7/40 ,  H01L21/0273

    摘要： The present invention provides a double photolithography method in which, after a first photoresist pattern including a crosslinkable agent is formed on a semiconductor substrate, a crosslinkage is formed in a molecular structure of the first photoresist pattern. A second photoresist film may be formed on a surface of the semiconductor substrate on which the crosslinked first photoresist patterns are formed. Second photoresist patterns may be formed by exposing, post-exposure baking, and developing the second photoresist film.

    摘要翻译： 本发明提供一种双光刻方法，其中在半导体衬底上形成包括可交联剂的第一光致抗蚀剂图案之后，在第一光致抗蚀剂图案的分子结构中形成交联。 可以在其上形成有交联的第一光致抗蚀剂图案的半导体衬底的表面上形成第二光致抗蚀剂膜。 可以通过曝光，曝光后烘烤和显影第二光致抗蚀剂膜来形成第二光致抗蚀剂图案。

    Focus monitoring masks having multiple phase shifter units and methods for fabricating the same
    8.
    发明申请
    Focus monitoring masks having multiple phase shifter units and methods for fabricating the same 审中-公开
    具有多个移相器单元的聚焦监视掩模及其制造方法

    公开(公告)号：US20060115746A1

    公开(公告)日：2006-06-01

    申请号：US11280606

    申请日：2005-11-16

    申请人： Sung-Won Choi ,  Suk-joo Lee ,  Ho-chul Kim ,  Han-ku Cho ,  Sang-gyun Woo

    发明人： Sung-Won Choi ,  Suk-joo Lee ,  Ho-chul Kim ,  Han-ku Cho ,  Sang-gyun Woo

    IPC分类号： G03C5/00 ,  G03F1/00

    CPC分类号： G03F1/28 ,  G03F1/44 ,  G03F7/70641

    摘要： A focus monitoring mask includes a transparent substrate, e.g., a quartz layer. A light blocking film, e.g., a chromium-containing film, is disposed on the transparent substrate and has an opening therein. A transparent unit is disposed in a portion of the substrate exposed by the opening. The transparent unit includes a first phase shifter, a second phase shifter and a third phase shifter arranged adjacently in order of amount of phase shift. The second phase shifter is configured to provide an about 180° phase difference with respect to the first phase shifter. The third phase shifter is configured to provide a phase difference other than about 0° and about 180° with respect to the first phase shifter. The transparent unit may further include a fourth phase shifter having a fourth phase difference with respect to the first phase shifter that differs from about 0°, about 180° and the phase difference provided by the third phase shifter.

    摘要翻译： 焦点监视掩模包括透明衬底，例如石英层。 遮光膜例如含铬膜设置在透明基板上并具有开口。 透明单元设置在由开口暴露的基板的一部分中。 透明单元包括第一移相器，第二移相器和第三移相器，其以相移量的顺序相邻布置。 第二移相器被配置为相对于第一移相器提供约180°的相位差。 第三移相器被配置为相对于第一移相器提供除了约0°和约180°之外的相位差。 透明单元还可以包括相对于第一移相器具有第四相位差的第四移相器，其不同于约0°，约180°以及由第三移相器提供的相位差。

    Semiconductor device having vertical channel transistor
    9.
    发明申请
    Semiconductor device having vertical channel transistor 审中-公开
    具有垂直沟道晶体管的半导体器件

    公开(公告)号：US20070284623A1

    公开(公告)日：2007-12-13

    申请号：US11802647

    申请日：2007-05-24

    申请人： Sang-Jin Kim ,  Gi-sung Yeo ,  Joon-soo Park ,  Han-ku Cho ,  Sang-gyun Woo ,  Min-jong Hong

    发明人： Sang-Jin Kim ,  Gi-sung Yeo ,  Joon-soo Park ,  Han-ku Cho ,  Sang-gyun Woo ,  Min-jong Hong

    IPC分类号： H01L29/76 ,  H01L29/745

    CPC分类号： H01L27/0207 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

    摘要： A semiconductor device includes a substrate, and a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar extending from the substrate and including a channel portion, wherein the odd columns include active pillars spaced at a first pitch, the first pitch being determined in the column direction, the even columns include active pillars spaced at the first pitch, the even rows include active pillars spaced at a third pitch, the third pitch being determined in the row direction the odd rows include active pillars spaced at the third pitch, and active pillars in the even columns are offset by a second pitch from active pillars in the odd columns, the second pitch being determined in the column direction.

    摘要翻译： 半导体器件包括衬底和布置成交替的偶数行和奇数行以及交替的偶数和奇数列的多个有源柱，每个有源柱从衬底延伸并且包括沟道部分，其中奇数列包括有源柱 以第一间距间隔开，第一间距是在列方向上确定的，偶数列包括以第一节距间隔开的活动柱，偶数行包括以第三节距间隔开的有效柱，第三间距在行方向上确定 奇数行包括在第三间距处间隔开的活动柱，并且偶数列中的活动柱由奇数列中的活动柱偏移第二间距，第二间距在列方向上确定。

    Method of forming trench in semiconductor device
    10.
    发明授权
    Method of forming trench in semiconductor device 失效
    在半导体器件中形成沟槽的方法

    公开(公告)号：US07259065B2

    公开(公告)日：2007-08-21

    申请号：US11080891

    申请日：2005-03-16

    申请人： Doo-hoon Goo ,  Si-hyeung Lee ,  Han-ku Cho ,  Sang-gyun Woo ,  Gi-sung Yeo

    发明人： Doo-hoon Goo ,  Si-hyeung Lee ,  Han-ku Cho ,  Sang-gyun Woo ,  Gi-sung Yeo

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10876 ,  H01L21/3083 ,  H01L27/0207

    摘要： There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of a first active region in a lateral direction, and also across another second active region in parallel with the first active region in a diagonal direction, and the extension is cut not to reach an isolation region between two third active regions that are in parallel with the second active region in a diagonal direction, and have noses facing each other in a longitudinal direction, and the layout includes an alignment of a plurality of open regions, which are discontinuously aligned. An etch mask is formed using the layout, and a semiconductor substrate is etched using the etch mask, and a trench for a recessed channel is formed on the active region.

    摘要翻译： 提供了一种形成用于晶体管的凹槽的沟槽的方法及其布局。 根据本发明的一个方面的凹陷通道的布局被形成为使得开放区域跨越横向方向上的第一有源区域中的至少一个延伸，并且还跨越与第一活性物体平行的另一个第二有源区域 区域，并且延伸部被切割成不能在对角线方向上到达与第二有源区域平行的两个第三有源区域之间的隔离区域，并且在纵向方向上具有彼此面对的鼻子，并且布局 包括不连续对准的多个开放区域的对准。 使用布局形成蚀刻掩模，并且使用蚀刻掩模蚀刻半导体衬底，并且在有源区上形成用于凹陷沟道的沟槽。