Bi-directional floating gate nonvolatile memory
    61.
    发明授权
    Bi-directional floating gate nonvolatile memory 有权
    双向浮动非易失性存储器

    公开(公告)号:US06747896B2

    公开(公告)日:2004-06-08

    申请号:US10140527

    申请日:2002-05-06

    申请人: Sau Ching Wong

    发明人: Sau Ching Wong

    IPC分类号: G11C1604

    摘要: A memory transistor has a pair of separate floating gates overlying end regions of a channel and a control gate that overlies the floating gates and a central region of the channel. The memory transistor effectively operates as a pair of floating gate transistors with an intervening select transistor. Each floating gate can be charged to store a distinct binary, analog, or multi-bit value. The direction of the channel current controls which floating gate receives channel hot electron injection during programming and which floating gate state is sensed during reading. A read operation biases the word line higher that the threshold voltage used to store data and compares the resulting channel to reference currents to identify a stored binary, analog, or multi-bit value. The threshold voltage range can include negative threshold voltages, which increases the available range for multi-bit-per-floating gate storage. The memory transistors can be integrated into a contactless array architecture having approximately one global bit/virtual ground line for every four floating gates along a row.

    摘要翻译: 存储晶体管具有覆盖通道的端部区域的一对分离的浮动栅极和覆盖在浮动栅极和沟道的中心区域上的控制栅极。 存储晶体管有效地作为具有中间选择晶体管的一对浮栅晶体管工作。 每个浮动栅极都可以被充电以存储不同的二进制,模拟或多位值。 通道电流的方向控制哪个浮动栅极在编程期间接收通道热电子注入,并且在读取期间感测哪个浮动栅极状态。 读取操作将字线偏置为用于存储数据的阈值电压较高,并将所得到的通道与参考电流进行比较,以识别存储的二进制,模拟或多位值。 阈值电压范围可以包括负阈值电压,这增加了多位逐浮栅存储的可用范围。 存储器晶体管可以被集成到具有大约一个全局位/虚拟接地线的非接触阵列结构中,每四个沿着一行的浮动栅极。

    Memory with offset bank select cells at opposite ends of buried diffusion lines
    62.
    发明授权
    Memory with offset bank select cells at opposite ends of buried diffusion lines 有权
    存储器在掩埋扩散线的两端的偏移库选择单元

    公开(公告)号:US06731539B1

    公开(公告)日:2004-05-04

    申请号:US10407894

    申请日:2003-04-04

    申请人: Sau Ching Wong

    发明人: Sau Ching Wong

    IPC分类号: G11C1604

    摘要: A compact contactless Flash memory architecture has memory cells instead of isolation regions between adjacent diffused lines in rows of a bank and thereby increases the density of memory cells in the bank when compared to prior architectures. Diffused lines in the bank can be used as virtual ground lines or as bit lines depending on which column of the bank is selected for access. The architecture includes about half as many metal lines as diffused lines, and most bank select cells operate to connect respective metal lines to respective pairs of diffused lines.

    摘要翻译: 紧凑型非接触式闪速存储器架构具有存储器单元,而不是存储体中行的相邻扩散线之间的隔离区域,从而与现有架构相比增加了存储体中的存储器单元的密度。 银行中的扩散线可以用作虚拟接地线或者作为位线,这取决于银行的哪一列被选择进行访问。 该架构包括大约一半的金属线作为扩散线,并且大多数银行选择单元操作以将相应的金属线连接到相应的扩散线对。

    Flash memory array partitioning architectures
    63.
    发明授权
    Flash memory array partitioning architectures 有权
    闪存阵列分区架构

    公开(公告)号:US06614685B2

    公开(公告)日:2003-09-02

    申请号:US09927693

    申请日:2001-08-09

    申请人: Sau Ching Wong

    发明人: Sau Ching Wong

    IPC分类号: G11C1604

    摘要: A Flash memory employs uniform-size blocks in array planes and has separate read and write paths connected to the array planes. The read path can read from one array plane while the write path writes in another array plane and one or more blocks are being erased. The uniform block size permits a symmetric layout and provides maximum flexibility in storage of data, code, and parameters. The uniform block size also allows spare blocks in the array planes to replace of any defective blocks. A redundancy system for the Flash memory uses a CAM and a RAM for address comparison and substitution to replace addresses corresponding to defective memory elements. To reduce access delays, part of the input address such as the row address goes directly to decoders, while another part of the input address such as the block address goes to the CAM array.

    摘要翻译: 闪存在阵列平面中使用均匀大小的块,并且具有连接到阵列平面的单独的读取和写入路径。 读路径可以从一个阵列平面读取,而写入路径写入另一个阵列平面,并且一个或多个块正在被擦除。 均匀块大小允许对称布局,并且在数据,代码和参数的存储方面提供最大的灵活性。 统一块大小还允许阵列平面中的备用块替换任何有缺陷的块。 闪存的冗余系统使用CAM和RAM进行地址比较和替换来替换与缺陷存储器元件相对应的地址。 为了减少访问延迟,诸如行地址的输入地址的一部分直接转换为解码器,而诸如块地址的输入地址的另一部分转到CAM阵列。

    Optimized lambda and compression temperature control for compression ignition engines
    64.
    发明授权
    Optimized lambda and compression temperature control for compression ignition engines 失效
    压缩式点火发动机优化的λ和压缩温度控制

    公开(公告)号:US06273076B1

    公开(公告)日:2001-08-14

    申请号:US08991413

    申请日:1997-12-16

    IPC分类号: E02D4104

    摘要: The performance of a compression ignition internal combustion engine is improved by optimizing excess air ratio (lambda) and/or intake air charge temperature (ACT) on a full time, full range basis. The basic procedure is to first determine the desired or optimum lambda and then to control ACT and intake manifold absolute pressure (MAP) to maintain them at the optimum values for the fuel quantity required at a particular operating point. This approach allows control of both temperature and pressure of the air entering the engine. Full range control requires that lambda and ACT be controlled both upward and downward to achieve optimal engine performance. Control of both lambda and ACT is further enhanced through the use of a supercharger with adjustable input power installed in series with a standard turbocharger compressor of the engine. Supercharger control may if desired be supplemented with turbo air bypass (TAB) control, turbocharger variable area nozzle or wastegate, turboexpander control, and intake and exhaust valve control including skip fire of both fuel and air. The essence of optimized lambda control is to measure the physical properties of the working fluid in the intake manifold, exhaust manifold, or both, compute the actual value of lambda, and compare that actual value with an optimum value for the prevailing engine operating conditions. This comparison yields an error signal which is then used to control the magnitude of the required adjustment in turbocharger pressure or other engine operating parameter.

    摘要翻译: 通过在全时间,全范围的基础上优化过量空气比(λ)和/或进气充气温度(ACT)来提高压缩点火内燃机的性能。 基本步骤是首先确定所需的或最佳的λ,然后控制ACT和进气歧管绝对压力(MAP),以将它们保持在特定工作点所需的燃料量的最佳值。 这种方法允许控制进入发动机的空气的温度和压力。 全范围控制要求将λ和ACT向上和向下控制,以实现最佳的发动机性能。 通过使用具有与发动机的标准涡轮增压器压缩机串联安装的可调输入功率的增压器来进一步增强对lambda和ACT的控制。 如果需要,增压器控制可以补充涡轮空气旁路(TAB)控制,涡轮增压器可变区域喷嘴或废气门,涡轮膨胀机控制以及进气和排气阀控制,包括燃料和空气的跳火。 优化的λ控制的本质是测量进气歧管,排气歧管或两者中的工作流体的物理性质,计算λ的实际值,并将该实际值与当前发动机运行条件的最佳值进行比较。 该比较产生误差信号,然后将其用于控制​​涡轮增压器压力或其它发动机运行参数中所需调整的大小。

    Bit line sense amplifier for programmable logic devices
    65.
    发明授权
    Bit line sense amplifier for programmable logic devices 失效
    用于可编程逻辑器件的位线读出放大器

    公开(公告)号:US4899070A

    公开(公告)日:1990-02-06

    申请号:US218556

    申请日:1988-07-13

    IPC分类号: G11C16/26

    CPC分类号: G11C16/26

    摘要: In a programmable logic device, switching speed is improved by preventing the bit line potential from going excessively close to ground even when large numbers of word line connections to the ground conductor are made. In addition, bit line pull up to logic 1 is effected more rapidly (without retarding bit line pull down to logic 0) by having two transistors connected in parallel with one another between the reference potential source and the bit line. One of these transistors is on all the time providing a relatively small leakage current. The other transistor is on only while the bit line is at logic 0, thereby speeding pull up to logic 1 and then shutting off so as not to impede subsequent return to logic 0.

    摘要翻译: 在可编程逻辑器件中,即使当进行大量与接地导体的字线连接时,也可以通过防止位线电位过分靠近接地而提高开关速度。 此外,通过使两个晶体管在参考电位源和位线之间彼此并联连接,上升到逻辑1的位线更快地实现(不将位线下拉到逻辑0)。 这些晶体管中的一个始终提供相对较小的漏电流。 另一个晶体管只在位线处于逻辑0时导通,从而加速上拉至逻辑1,然后关断,以免后续返回到逻辑0。

    Programmable logic devices with spare circuits for use in replacing
defective circuits
    66.
    发明授权
    Programmable logic devices with spare circuits for use in replacing defective circuits 失效
    具有备用电路的可编程逻辑器件用于更换有缺陷的电路

    公开(公告)号:US4899067A

    公开(公告)日:1990-02-06

    申请号:US222832

    申请日:1988-07-22

    IPC分类号: H03K19/177 G06F11/20

    摘要: A programmable logic device having a plurality of word lines and a plurality of bit lines, each of which is programmably interconnectable to at least one of the word lines for producing on each bit line a signal which is a logical function of the signal or signals on the word line or lines to which that bit line is interconnected. The logic device further includes at least one spare word line and/or bit line for use in the event that one of the regular lines of the same kind in defective. When the spare line is to be used, the device is preprogrammed to automatically redirect all signals intended for the bad line to another line, thereby putting the spare line into use. The signals thus automatically redirected include both the signals used during program mode to selectively interconnect the word lines and bit lines and the data signals subsequently processed during normal operation of the device.

    METHOD FOR DETERMINING INTERACTION SITES BETWEEN BIOSEQUENCES

    公开(公告)号:US20210304842A1

    公开(公告)日:2021-09-30

    申请号:US17345699

    申请日:2021-06-11

    IPC分类号: G16B20/30 G16B20/00 G16B40/00

    摘要: A method and system for determining interaction sites between biosequences is described herein. A dataset of contact data for a plurality of biomolecule pairs is obtained to account their frequency of occurrence. Statistical weights are obtained for each frequency of occurrence. A statistical vector space (SRV) is decomposed through principal component decomposition. The r-vectors of the SRV are re-projected back to a new SRV with a new set of SR coordinates. A feature vector is generated and inputted into a predictor for outputting a likelihood of an interaction site. A method and system for determining significant attribute-value associations (AVAs) from relational datasets is also described. A frequency of occurrence of attribute value pairs and statistical weights may be obtained for each frequency of occurrence. Principal component decomposition and re-projection of AVA vectors may also be performed. The disentangle SR of AVAs could be used to identify AVA related to subgroups/classes.

    SYSTEM AND METHOD FOR DETERMINING DATA PATTERNS USING DATA MINING

    公开(公告)号:US20200301949A1

    公开(公告)日:2020-09-24

    申请号:US16823627

    申请日:2020-03-19

    IPC分类号: G06F16/28 G06K9/62

    摘要: A system and method for processing relational datasets are provided, the method may include: retrieving a relational dataset containing a plurality of entities and a plurality of attribute values; constructing an entity address table, based on the relational dataset, wherein the entity address table contains the plurality of attribute values, and each of the plurality of attribute values is associated with one or more entity addresses in the relational dataset; generating a frequency table, based on the entity address table, wherein the frequency table contains one or more cardinality values; generating a SR vector space table comprising a plurality of SR values for the plurality of a pair of attribute values; generating PCs and their corresponding RSRVs through disentangling SRV into a plurality of disentangled spaces (DS); selecting from the plurality of DS, a subset of DS; and generating one or more patterns based on the plurality of DS.

    Writing Aid
    70.
    发明申请
    Writing Aid 审中-公开

    公开(公告)号:US20180047299A1

    公开(公告)日:2018-02-15

    申请号:US15675071

    申请日:2017-08-11

    IPC分类号: G09B11/02 B33Y80/00

    CPC分类号: G09B11/02 B33Y80/00

    摘要: A writing aid is provided which may be used to promote better form for the hand for the user. It may be used to teach young persons or individuals with disabilities who are first learning to write, and may also be used to provide comfort and better ergonomics to individuals who must write frequently. The writing aid is designed to be compatible with different writing apparatuses with carrying thicknesses, ranging from relatively thin pencil crayons to relatively thick markers.