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102 条记录 (耗时 0.026 秒)

    MEMORY SYSTEM
    61.
    发明申请
    MEMORY SYSTEM 有权
    记忆系统

    公开(公告)号：US20100205353A1

    公开(公告)日：2010-08-12

    申请号：US12559983

    申请日：2009-09-15

    申请人： Hironobu MIYAMOTO ,  Hajime Yamazaki ,  Shinji Yonezawa

    发明人： Hironobu MIYAMOTO ,  Hajime Yamazaki ,  Shinji Yonezawa

    IPC分类号： G06F12/00 ,  G06F12/02

    CPC分类号： G06F12/0246 ,  G06F11/1471 ,  G06F2201/84 ,  G06F2212/7201

    摘要： A memory system according to an embodiment of the present invention comprises: a log overflow control unit that, when a third condition in which a second log accumulated in a log storage area exceeds a set value is satisfied, stops a recording operation of the second log in the log storage area by a log recording unit and causes a log recording unit to perform an update operation of a second management table in a master table and a recording operation of a first log in the log storage area, and that, when a first condition is satisfied next time, prohibits a commit operation by a log reflecting unit and causes a snapshot storing unit to perform a snapshot storing operation.

    摘要翻译： 根据本发明实施例的存储器系统包括：日志溢出控制单元，当满足累积在日志存储区域中的第二对数超过设定值的第三条件时，停止第二日志的记录操作 在日志记录单元的日志存储区域中，使日志记录单元执行主表中的第二管理表的更新操作和日志存储区中的第一日志的记录操作，并且当第一 条件下一次被满足时，禁止日志反射单元的提交操作，并使快照存储单元执行快照存储操作。

    Field Effect Transistor
    62.
    发明申请
    Field Effect Transistor 审中-公开
    场效应晶体管

    公开(公告)号：US20100155779A1

    公开(公告)日：2010-06-24

    申请号：US11992755

    申请日：2006-09-28

    申请人： Yasuhiro Murase ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Kouji Matsunaga ,  Hironobu Miyamoto

    发明人： Yasuhiro Murase ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Kouji Matsunaga ,  Hironobu Miyamoto

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/405 ,  H01L29/66462

    摘要： In a field effect transistor, a Group III nitride semiconductor layer structure containing a hetero junction, a source electrode 101 and a drain electrode 103 formed apart from each other over the Group III nitride semiconductor layer structure, and a gate electrode 102 disposed between these electrodes, are provided. Over the surface of the Group III nitride semiconductor layer structure, a SiO2 film 122 containing oxygen as a constitutive element is provided, in contact with both side faces of the gate electrode 102. Over the surface of the Group III nitride semiconductor layer structure, a SiN film 121 is provided so as to cover the region between the SiO2 film 122 and the source electrode 101, and the region between the SiO2 film 122 and the drain electrode 103. The SiN film 121 is composed of a material different from that composing the SiO2 film 122, and contains nitrogen as a constitutive element.

    摘要翻译： 在场效应晶体管中，包含异质结的III族氮化物半导体层结构，在III族氮化物半导体层结构上彼此分开形成的源电极101和漏极103以及设置在这些电极之间的栅极102 ，提供。 在III族氮化物半导体层结构的表面上，提供含有氧作为构成元素的SiO 2膜122，与栅电极102的两个侧面接触。在III族氮化物半导体层结构的表面上， SiN膜121被设置为覆盖SiO 2膜122和源电极101之间的区域以及SiO 2膜122和漏电极103之间的区域。SiN膜121由与不同于构成 SiO 2膜122，并且含有氮作为构成元素。

    FIELD EFFECT TRANSISTOR, AND MULTILAYERED EPITAXIAL FILM FOR USE IN PREPARATION OF FIELD EFFECT TRANSISTOR
    65.
    发明申请
    FIELD EFFECT TRANSISTOR, AND MULTILAYERED EPITAXIAL FILM FOR USE IN PREPARATION OF FIELD EFFECT TRANSISTOR 有权
    场效应晶体管和用于制备场效应晶体管的多层外延膜

    公开(公告)号：US20090045438A1

    公开(公告)日：2009-02-19

    申请号：US12159599

    申请日：2006-10-25

    申请人： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

    发明人： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

    IPC分类号： H01L29/205 ,  H01L29/80

    CPC分类号： H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

    摘要： In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

    摘要翻译： 在III族氮化物型场效应晶体管中，本发明通过缓冲层中的残留载流子的传导来减少漏电流成分，并且可以实现击穿电压的提高，并提高载流子限制效应（载流子限制） 提高夹断特性的通道（抑制短路效应）。 例如，当将本发明应用于GaN型场效应晶体管时，除了沟道层的GaN之外，使用其中铝组成逐渐或逐步朝向顶部的组分调制（组成梯度）AlGaN层用作 缓冲层（杂质缓冲液）。 对于要制备的FET的栅极长度Lg，选择电子供给层和沟道层的层厚度的和a以满足Lg / a> = 5，并且在这种情况下， 在不超过5倍（约500）的范围内选择通道层，只要在室温下积聚在通道层中的二维电子气的德布罗意波长即可。

    Schottky Electrode of Nitride Semiconductor Device and Process for Production Thereof
    67.
    发明申请
    Schottky Electrode of Nitride Semiconductor Device and Process for Production Thereof 审中-公开
    氮化硅半导体器件的肖特基电极及其制造方法

    公开(公告)号：US20080006853A1

    公开(公告)日：2008-01-10

    申请号：US11571816

    申请日：2005-07-08

    申请人： Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Okamoto ,  Masaaki Kuzuhara ,  Takashi Inoue ,  Koji Hataya

    发明人： Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Okamoto ,  Masaaki Kuzuhara ,  Takashi Inoue ,  Koji Hataya

    IPC分类号： H01L29/47 ,  H01L21/283 ,  H01L29/812

    CPC分类号： H01L29/475 ,  H01L29/2003 ,  H01L29/812

    摘要： The present invention provides a Schottky electrode for a nitride semiconductor device having a high barrier height, a low leak current performance and a low resistance and being thermally stable, and a process for production thereof. The Schottky electrode for a nitride semiconductor has a layered structure that comprises a copper (Cu) layer being in contact with the nitride semiconductor and a first electrode material layer formed on the copper (Cu) layer as an upper layer. As the first electrode material, a metal material which has a thermal expansion coefficient smaller than the thermal expansion coefficient of copper (Cu) and starts to undergo a solid phase reaction with copper (Cu) at a temperature of 400° C. or higher is employed.

    摘要翻译： 本发明提供了一种用于氮化物半导体器件的肖特基电极，其具有高势垒高度，低漏电流性能和低电阻并且是热稳定的，以及其制造方法。 用于氮化物半导体的肖特基电极具有包括与氮化物半导体接触的铜（Cu）层和形成在作为上层的铜（Cu）层上的第一电极材料层的层状结构。 作为第一电极材料，在400℃以上的温度下开始与铜（Cu）的热膨胀系数小于铜（Cu）的热膨胀系数并开始与铜（Cu）的固相反应的金属材料为 雇用。

    Computer system having an interrupt handler
    70.
    发明授权
    Computer system having an interrupt handler 失效
    具有中断处理程序的计算机系统

    公开(公告)号：US06223246B1

    公开(公告)日：2001-04-24

    申请号：US09219790

    申请日：1998-12-23

    申请人： Hironobu Miyamoto

    发明人： Hironobu Miyamoto

    IPC分类号： G06F1324

    CPC分类号： G06F13/24

    摘要： Referred to is a flag pattern in an interrupt activation condition flag storing unit which stores an event as an interrupt activation condition flag. As a result thereof, it is determined whether or no the flag pattern exists in an operational key description storing unit which stores the position for the operation corresponding to the flag pattern n the interrupt activation condition flag storing unit. As a result of the determination, an interrupt process is performed in accordance with an operational description storing unit which stores a process corresponding to the flag pattern if the pattern exits. Thereafter, bit for the flag corresponding to the executed process is cleared out.

    摘要翻译： 被称为中断激活条件标志存储单元中的标志模式，其将事件存储为中断激活条件标志。 作为其结果，确定在操作密钥描述存储单元中是否存在标志模式，该操作密钥描述存储单元存储与中断激活条件标志存储单元相对应的标志模式n的操作的位置。 作为确定的结果，根据操作描述存储单元执行中断处理，该操作描述存储单元如果模式退出则存储对应于标志模式的处理。 此后，清除与执行处理相对应的标志的位。