公开(公告)号：US20110317482A1

公开(公告)日：2011-12-29

申请号：US13110399

申请日：2011-05-18

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C8/08 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0071

Abstract: A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word line driver is minimized by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby.

Abstract translation: 一种用于改善子字线响应的方法包括生成由至少一个用户参数确定的可变衬底偏置。 可变衬底偏置被施加到存储器的所选子块中的子字线驱动器。 通过修改子字线驱动器的可变衬底偏置来改变子字线驱动器的跨导，从而最小化与子字线驱动器通信的子字线上的电压干扰。

公开(公告)号：US08060691B2

公开(公告)日：2011-11-15

申请号：US13022166

申请日：2011-02-07

Applicant: Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

Inventor： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

IPC: G06F13/00 ,  G06F13/28 ,  G06F3/00 ,  G06F5/00

CPC classification number: G06F13/4243 ,  G06F13/4247

Abstract: An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

Abstract translation: 提供了一种页面编程操作的装置和方法。 当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本 。 在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。 由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

公开(公告)号：US20110261613A1

公开(公告)日：2011-10-27

申请号：US13044701

申请日：2011-03-10

Applicant: Hong Beom PYEON

Inventor： Hong Beom PYEON

IPC: G11C11/00

CPC classification number: G11C13/0028 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2213/72

Abstract: A phase change memory is disclosed. The phase change memory has a plurality of block units. The block units are alternately selected. The alternate block unit selection suppresses peak current ground bouncing on sub-wordline and connected ground line through sub-wordline driver transistor. An alternate bitline selection avoids adjacent cell heating interference in the selected block unit.

Abstract translation: 公开了一种相变存储器。 相变存储器具有多个块单元。 交替选择块单元。 替代块单元选择抑制子字线上的峰值电流接地跳变，并通过子字线驱动晶体管抑制连接的地线。 替代位线选择避免了所选块单元中的相邻单元加热干扰。

公开(公告)号：US20110258399A1

公开(公告)日：2011-10-20

申请号：US13168157

申请日：2011-06-24

Applicant: Shuji SUMI ,  Hong Beom PYEON

Inventor： Shuji SUMI ,  Hong Beom PYEON

IPC: G06F12/00

CPC classification number: G06F13/1694 ,  G06F13/4243

Abstract: A memory controller is unaware of device types (DTs) of a plurality (N) of series-connected memory devices in an interconnection configuration. Possible DTs include, e.g., random access memories and Flash memories. First, the memory controller sends a specific DT (“don't care”) and an initial number of binary code to the first device of the interconnection configuration and the binary code is propagated through the devices. Each device performs a “+1” calculation regardless of the DT. The last device provides the memory controller with Nד+1” from which the memory controller can obtain the number N of devices in the interconnection configuration. Thereafter, the memory controller sends a search number (SN) of binary code and a search DT for DT matching that propagate through the devices. Each device performs DT match determination of “previous match”, “present match” and “don't care match”. Based on the match determination, the SN and search DT are or not modified. The modified or non-modified SN and DT are propagated through the devices. Such processes are repeated. From the propagated SN and DT and the previously recognized number of the devices, the memory controller can identify the DT of each device in the interconnection configuration.

Abstract translation: 存储器控制器不知道互连配置中的多个（N）个串联存储器件的设备类型（DT）。 可能的DT包括例如随机存取存储器和闪速存储器。 首先，存储器控制器向互连配置的第一设备发送特定的DT（“不关心”）和初始数量的二进制代码，并且通过设备传播二进制代码。 每个设备不管DT是否执行“+1”计算。 最后一个设备为内存控制器提供Nד+1”，内存控制器可以从中获取互连配置中的设备数量N。 此后，存储器控制器发送二进制码的搜索号（SN）和通过设备传播的用于DT匹配的搜索DT。 每个设备执行“前一个匹配”，“当前匹配”和“不关心匹配”的DT匹配确定。 基于匹配确定，SN和搜索DT是否被修改。 经修改或未修改的SN和DT通过设备传播。 重复这些过程。 从传播的SN和DT以及先前识别的设备数量，存储器控制器可以识别互连配置中每个设备的DT。

公开(公告)号：US20110258366A1

公开(公告)日：2011-10-20

申请号：US13023838

申请日：2011-02-09

Applicant: Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

Inventor： Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

IPC: G06F12/00

CPC classification number: G11C7/1063 ,  G11C16/06

Abstract: Status indication in a system having a plurality of memory devices is disclosed. A memory device in the system includes a plurality of data pins for connection to a data bus. The memory device also includes a status pin for connection to a status line that is independent from the data bus. The memory device also includes first circuitry for generating, upon completion of a memory operation having a first duration, a strobe pulse of a second duration much shorter than the first duration. The strobe pulse provides an indication of the completion of the memory operation. The memory device also includes second circuitry for outputting the strobe pulse onto the status line via the status pin.

Abstract translation: 公开了具有多个存储器件的系统中的状态指示。 系统中的存储器件包括用于连接到数据总线的多个数据引脚。 存储器件还包括用于连接到独立于数据总线的状态线的状态引脚。 存储器件还包括第一电路，用于在完成具有第一持续时间的存储器操作时产生比第一持续时间短得多的第二持续时间的选通脉冲。 选通脉冲提供存储器操作完成的指示。 存储器件还包括用于经由状态引脚将选通脉冲输出到状态线上的第二电路。

公开(公告)号：US20110255339A1

公开(公告)日：2011-10-20

申请号：US13171667

申请日：2011-06-29

Applicant: Jin-Ki KIM ,  Hong Beom PYEON

Inventor： Jin-Ki KIM ,  Hong Beom PYEON

IPC: G11C16/08

CPC classification number: G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/4243 ,  G11C5/066 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2207/107 ,  G11C2216/30

Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Abstract translation: 公开了一种用于控制半导体存储器中的多个串行数据链路接口和多个存储体之间的数据传输的装置，系统和计算机实现的方法。 在一个示例中，公开了具有多个链路和存储体的闪存器件，其中链路独立于存储体。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。 此外，描述了虚拟多链路配置，其中使用单个链路来模拟多个链路。

公开(公告)号：US20110222350A1

公开(公告)日：2011-09-15

申请号：US13114523

申请日：2011-05-24

Applicant: Hong Beom PYEON

Inventor： Hong Beom PYEON

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C2211/5642 ,  G11C2211/5647

Abstract: An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch.

Abstract translation: 提供了使用两级MLC（多级单元）操作的诸如页面缓冲器的访问缓冲器，用于写入诸如Flash的非易失性存储器。 访问缓冲器具有用于临时存储要写入的数据的第一锁存器。 提供第二锁存器用于从作为两级写入操作的一部分的数据从存储器读取数据。 第二个锁存器具有从存储器读取时参与锁存功能的反相器。 相同的反相器用于产生正被写入第一锁存器的输入信号的补码，结果是使用双端输入来写入第一锁存器。

公开(公告)号：US07991925B2

公开(公告)日：2011-08-02

申请号：US12025177

申请日：2008-02-04

Applicant: Shuji Sumi ,  Hong Beom Pyeon

Inventor： Shuji Sumi ,  Hong Beom Pyeon

IPC: G06F3/00

CPC classification number: G06F13/1694 ,  G06F13/4243

Abstract: A memory controller is unaware of device types (DTs) of a plurality (N) of series-connected memory devices in an interconnection configuration. Possible DTs include, e.g., random access memories and Flash memories. First, the memory controller sends a specific DT (“don't care”) and an initial number of binary code to the first device of the interconnection configuration and the binary code is propagated through the devices. Each device performs a “+1” calculation regardless of the DT. The last device provides the memory controller with Nד+1” from which the memory controller can obtain the number N of devices in the interconnection configuration. Thereafter, the memory controller sends a search number (SN) of binary code and a search DT for DT matching that propagate through the devices. Each device performs DT match determination of “previous match”, “present match” and “don't care match”. Based on the match determination, the SN and search DT are or not modified. The modified or non-modified SN and DT are propagated through the devices. Such processes are repeated. From the propagated SN and DT and the previously recognized number of the devices, the memory controller can identify the DT of each device in the interconnection configuration.

Abstract translation: 存储器控制器不知道互连配置中的多个（N）个串联存储器件的设备类型（DT）。 可能的DT包括例如随机存取存储器和闪速存储器。 首先，存储器控制器向互连配置的第一设备发送特定的DT（“不关心”）和初始数量的二进制代码，并且通过设备传播二进制代码。 每个设备不管DT是否执行“+1”计算。 最后一个设备为内存控制器提供Nד+1”，内存控制器可以从中获取互连配置中的设备数量N。 此后，存储器控制器发送二进制码的搜索号（SN）和通过设备传播的用于DT匹配的搜索DT。 每个设备执行“前一个匹配”，“当前匹配”和“不关心匹配”的DT匹配确定。 基于匹配确定，SN和搜索DT是否被修改。 经修改或未修改的SN和DT通过设备传播。 重复这些过程。 从传播的SN和DT以及先前识别的设备数量，存储器控制器可以识别互连配置中每个设备的DT。

公开(公告)号：US20110185086A1

公开(公告)日：2011-07-28

申请号：US13077168

申请日：2011-03-31

Applicant: Hong Beom PYEON ,  HakJune OH ,  Jin-Ki KIM ,  Shuji SUMI

Inventor： Hong Beom PYEON ,  HakJune OH ,  Jin-Ki KIM ,  Shuji SUMI

IPC: G06F3/00

CPC classification number: G11C16/20 ,  G11C8/12

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. In cases of different device types being separately provided to the interconnected devices, sequential IDs are generated in each of the different device types and also the total number of each device type are recognized. In a case of a “don't care” code is provided to the interconnected devices, sequential IDs are generated and also, the total number of the interconnected devices is recognized, regardless of the type differences.

Abstract translation: 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND，NOR和AND型闪存）串联连接。 每个设备都有其设备类型的设备类型信息。 包含在串行输入（SI）中的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。 生成的ID被传送到串行互连的另一个设备。 在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。 在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 在将不同设备类型分别提供给互连设备的情况下，在不同设备类型中的每一种中生成顺序ID，并且还识别每种设备类型的总数。 在向互连设备提供“不关心”代码的情况下，生成顺序ID，并且还识别互连设备的总数，而不管类型差异。

公开(公告)号：US07952929B2

公开(公告)日：2011-05-31

申请号：US12026825

申请日：2008-02-06

Applicant: Jin-Ki Kim ,  Hong Beom Pyeon

Inventor： Jin-Ki Kim ,  Hong Beom Pyeon

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to the selected memory cell, and then followed by the application of bitline data. After asymmetrical precharging and application of the programming voltage, all the selected memory cells will be set to a program inhibit state as they will be decoupled from the other memory cells in their respective NAND strings, and their channels will be locally boosted to a voltage effective for inhibiting programming. A VSS biased bitline will discharge the locally boosted channel to VSS, thereby allowing programming of the selected memory cell to occur. A VDD biased bitline will have no effect on the precharged NAND string, thereby maintaining a program inhibited state of that selected memory cell.

Abstract translation: 一种用于编程NAND闪存单元以最小化程序压力同时允许随机页面编程操作的方法。 该方法包括从正偏压的源极线不对称地预充电NAND串，同时位线与NAND串解耦，随后将编程电压施加到所选择的存储器单元，然后应用位线数据。 在非对称预充电和编程电压的施加之后，所有选定的存储单元将被设置为编程禁止状态，因为它们将与它们各自的NAND串中的其它存储单元分离，并且它们的通道将被局部升压到有效的电压 用于禁止编程。 VSS偏置位线将本地提升的通道放电到VSS，从而允许对所选存储单元进行编程。 VDD偏置位线对预充电NAND串不起作用，从而保持所选存储单元的程序禁止状态。