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    Self-correcting modular-redundancy-memory device
    61.
    发明授权
    Self-correcting modular-redundancy-memory device 有权

    公开(公告)号：US11527271B2

    公开(公告)日：2022-12-13

    申请号：US17466015

    申请日：2021-09-03

    Applicant: IHP GmbH—Innovations for High Performance Microelectronics / Leibniz-Institut für innovative Mikroelektronik

    Inventor： Oliver Schrape ,  Anselm Breitenreiter ,  Frank Vater ,  Milos Krstic

    IPC: G11C7/10 ,  G11C7/22 ,  H03K5/135 ,  H03K5/15

    Abstract: The invention is directed to a self-correcting modular-redundancy-memory device, comprising three bistable-memory elements and a majority voter. The bistable-memory elements receive respective binary data signal, clock signal, and a feedback signal. Each of the bistable-memory elements is configured, in response to the clock signal assuming a first value, to provide a binary output signal with an output-signal value correlated to a data-signal value of the data signal, and in response to the clock signal assuming a second clock-signal value, to provide the output signal with the output-signal value indicative of a current feedback-signal value of the feedback signal. The majority voter receives the output signals each of the bistable-memory elements and is configured to provide the feedback signal with the feedback-signal value indicative of that output-signal value taken on by a majority of the currently received output signals.

    DEVICE AND METHOD FOR MULTIPLICATION FOR IMPEDING SIDE-CHANNEL ATTACKS
    68.
    发明申请
    DEVICE AND METHOD FOR MULTIPLICATION FOR IMPEDING SIDE-CHANNEL ATTACKS 审中-公开

    公开(公告)号：US20170357484A1

    公开(公告)日：2017-12-14

    申请号：US15523977

    申请日：2015-11-06

    Applicant: IHP GmbH - Innovations for High Performance Micro- electronics/Leibniz-Institut Fur Innovative Mic..

    Inventor： Zoya Dyka ,  Peter Langendorfer

    IPC: G06F7/53 ,  H04L9/00

    CPC classification number: G06F7/5324 ,  G06F2207/7252 ,  G06F2207/7257 ,  H04L9/003 ,  H04L2209/08

    Abstract: A device for multiplying two bit sequences has a controller that selects and activates exactly one multiplier unit from a plurality of parallel multiplier units, according to a random signal. A partial multiplier unit shared by all the multiplier units receives and multiplies operands formed by the respectively activated multiplier unit. Each multiplier unit implements a different multiplication method with a respective selector unit that selects segments of the bit sequences to be multiplied, in accordance with a selection plan adapted to the respective multiplication method, to form operands from one or more segments and outputs the operands. The respective accumulation unit receives step by step partial products from the partial multiplier unit, accumulates the partial products in accordance with an accumulation plan adapted to the implemented multiplication method and matching the selection plan, and outputs the calculated product of after accumulation has been completed.

    Method for fabricating a bipolar transistor having self-aligned emitter contact
    69.
    发明授权
    Method for fabricating a bipolar transistor having self-aligned emitter contact 有权
    用于制造具有自对准发射极接触的双极晶体管的方法

    公开(公告)号：US09508824B2

    公开(公告)日：2016-11-29

    申请号：US14556352

    申请日：2014-12-01

    Applicant: IHP GmbH—Innovations for High Performance Microelectronics/Leibniz-Institut Fur Innovative Mikroelektronik

    Inventor： Alexander Fox ,  Bernd Heinemann ,  Steffen Marschmeyer

    IPC: H01L21/8249 ,  H01L29/66 ,  H01L21/8222 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/732 ,  H01L29/737

    CPC classification number: H01L29/66242 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7371

    Abstract: A method of producing a semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, the portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein the base connection region, aside from a seeding layer adjacent the substrate or a metallization layer adjacent a base contact, consists of a semiconductor material which differs in its chemical composition from the semiconductor material of the collector, the base and the emitter and in which the majority charge carriers of the first conductivity type have greater mobility compared thereto.

    Abstract translation: 一种制造半导体器件的方法，包括由第一导电类型的半导体材料制成并具有第一绝缘区域的衬底层和垂直双极晶体管，所述垂直双极晶体管具有由第二绝缘区域的单晶半导体材料制成的集电极的第一垂直部分 导电类型并且设置在第一绝缘区域的开口中，第二绝缘区域部分地位于集电体的第一垂直部分上并且部分地位于第一绝缘区域上，并且在集电体的区域中具有开口，其中开口第二绝缘区域 设置由单晶材料制成的集电体的垂直部分，该部分包括第二导电类型的内部区域，由第一导电类型的单晶半导体材料制成的基底，在横向方向上围绕基底的基底连接区域， 由第二导电类型的半导体材料制成的T形发射体及其结构 研磨基底连接区域，其中除了与基底相邻的接种层或与基底接触相邻的金属化层之外的基底连接区域由其化学组成与收集器的半导体材料不同的半导体材料组成，基底 并且其中与其相比，第一导电类型的多数电荷载流子具有更大的迁移率。

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