公开(公告)号：US08946869B2

公开(公告)日：2015-02-03

申请号：US13041003

申请日：2011-03-04

申请人： Dae-Suk Kim ,  Jong-Chern Lee ,  Chul Kim

发明人： Dae-Suk Kim ,  Jong-Chern Lee ,  Chul Kim

IPC分类号： H01L29/00 ,  H01L29/80 ,  H01L23/48 ,  H01L21/66 ,  G01R31/28 ,  H01L23/00

CPC分类号： H01L22/34 ,  G01R31/2853 ,  G01R31/2884 ,  H01L23/481 ,  H01L24/05 ,  H01L2225/06544 ,  H01L2225/06596 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.

摘要翻译： 在晶圆级别检测贯通硅通孔是否具有缺陷的集成电路。 集成电路包括：半导体衬底;通孔构造成形成在半导体衬底中以从半导体衬底的表面延伸到一定深度的通硅通孔，输出焊盘和电流通路提供单元，其被配置为提供电流， 在测试模式期间，在半导体衬底和贯穿硅通孔之间流动到输出焊盘。

公开(公告)号：US08829933B2

公开(公告)日：2014-09-09

申请号：US12836538

申请日：2010-07-14

申请人： Tae Sik Yun ,  Jong Chern Lee

发明人： Tae Sik Yun ,  Jong Chern Lee

IPC分类号： G01R31/20 ,  H01L21/66 ,  G11C29/00

CPC分类号： H01L22/34 ,  G11C29/006 ,  H01L2924/0002 ,  H01L2924/00

摘要： Various embodiments of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, a semiconductor apparatus may include a chip, scribe lanes disposed around the chip, and a probe test logic circuit for conducting a probe test on the chip. The probe test logic circuit is disposed on a portion of the scribe lanes.

摘要翻译： 公开了半导体装置和相关方法的各种实施例。 在一个示例性实施例中，半导体装置可以包括设置在芯片周围的芯片，划线，以及用于在芯片上进行探针测试的探针测试逻辑电路。 探针测试逻辑电路设置在划线的一部分上。

公开(公告)号：US20130241054A1

公开(公告)日：2013-09-19

申请号：US13604449

申请日：2012-09-05

申请人： Chul KIM ,  Jong Chern LEE

发明人： Chul KIM ,  Jong Chern LEE

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L21/76885 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16013 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

摘要： In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip.

摘要翻译： 在半导体装置中，包括贯通硅通孔的多个半导体芯片在垂直方向堆叠，其中形成在每个半导体芯片中的贯通硅通孔突出超过每个半导体芯片的高度。

公开(公告)号：US08436651B2

公开(公告)日：2013-05-07

申请号：US12624144

申请日：2009-11-23

申请人： Hyun-Su Yoon ,  Jong-Chern Lee

发明人： Hyun-Su Yoon ,  Jong-Chern Lee

IPC分类号： G06F7/38

CPC分类号： H04L7/02 ,  H04L7/0045

摘要： A command control circuit of a semiconductor integrated device includes a plurality of latches sequentially connected and receiving a command signal, and a plurality of selection switches configured to pass or to interrupt the command signal inputted to each one of the plurality of latches.

摘要翻译： 半导体集成装置的指令控制电路包括顺序地连接并接收命令信号的多个锁存器，以及被配置为通过或中断输入到多个锁存器中的每一个的指令信号的多个选择开关。

公开(公告)号：US08344783B2

公开(公告)日：2013-01-01

申请号：US12970623

申请日：2010-12-16

申请人： Jae Bum Ko ,  Jong Chern Lee ,  Sang Jin Byeon

发明人： Jae Bum Ko ,  Jong Chern Lee ,  Sang Jin Byeon

IPC分类号： H03H11/26

CPC分类号： H03K5/1506 ,  H03K5/05

摘要： A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal.

摘要翻译： 延迟电路包括：延迟单元，被配置为接收时钟信号，按预定时间间隔顺序地延迟输入信号，并输出多个第一延迟信号; 以及选择单元，被配置为基于一个或多个选择信号来选择所述多个第一延迟信号中的一个，并输出第二延迟信号。

公开(公告)号：US08223523B2

公开(公告)日：2012-07-17

申请号：US12650507

申请日：2009-12-30

申请人： Sin Hyun Jin ,  Jong Chern Lee

发明人： Sin Hyun Jin ,  Jong Chern Lee

IPC分类号： G11C5/02

CPC分类号： G11C5/04 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/00014

摘要： A semiconductor apparatus having a plurality of stacked chips includes: a through silicon via (TSV) configured to couple the plurality of chips together and configured to be coupled in series to a plurality of voltage drop units; a plurality of signal conversion units, each of which is configured to convert a voltage outputted from the voltage drop unit of the corresponding one of the plurality of chips to a digital code signal and provide the digital code signal as chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is configured to compare the chip identification signal with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips.

摘要翻译： 具有多个堆叠芯片的半导体装置包括：贯穿硅通孔（TSV），被配置为将多个芯片耦合在一起并且被配置为串联耦合到多个压降单元; 多个信号转换单元，每个信号转换单元被配置为将从多个芯片中的相应一个芯片的电压降单元输出的电压转换为数字代码信号，并将数字代码信号提供为对应的一个芯片识别信号 的多个芯片; 以及多个芯片选择信号生成单元，每个芯片选择信号生成单元被配置为将芯片识别信号与芯片选择识别信号进行比较，以生成多个芯片中相应的一个芯片的芯片选择信号。

公开(公告)号：US08107310B2

公开(公告)日：2012-01-31

申请号：US12650594

申请日：2009-12-31

申请人： Dae-Suk Kim ,  Jong-Chern Lee

发明人： Dae-Suk Kim ,  Jong-Chern Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40611 ,  G11C11/40618

摘要： A semiconductor memory device includes a bank having a plurality of mats, an address counting unit configured to receive an auto-refresh command consecutively applied at predetermined intervals corresponding to a number of the mats, and sequentially count an internal address in response to the auto-refresh command, and an address transferring unit configured to enable the plurality of mats in response to the auto-refresh command, and transfer the internal address to the plurality of mats at predetermined time intervals.

摘要翻译： 半导体存储器件包括具有多个垫的存储体，地址计数单元，被配置为接收以对应于所述垫的数量的预定间隔连续地施加的自动刷新命令，并且响应于所述自动刷新命令顺序计数内部地址， 刷新命令和地址传送单元，被配置为响应于所述自动刷新命令启用所述多个垫，并且以预定的时间间隔将所述内部地址传送到所述多个垫。

公开(公告)号：US20110272790A1

公开(公告)日：2011-11-10

申请号：US12833672

申请日：2010-07-09

申请人： Jun-Gi Choi ,  Jong-Chern Lee

发明人： Jun-Gi Choi ,  Jong-Chern Lee

IPC分类号： H01L23/544

CPC分类号： H01L22/32 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer includes at least one chip formed on a substrate, and a scribe line region surrounding the chip. The chip includes a device formation region, and a chip boundary region surrounding the device formation region and formed between the device formation region and the scribe line region. The chip boundary region includes a guard ring structure which physically separates the device formation region from the scribe line region. The guard ring structure includes a signal transfer element which transfers an electric signal between the device formation region and the scribe line region.

摘要翻译： 半导体晶片包括形成在基板上的至少一个芯片和围绕芯片的划线区域。 芯片包括器件形成区域和围绕器件形成区域并形成在器件形成区域和划线区域之间的芯片边界区域。 芯片边界区域包括将器件形成区域与划线区域物理分离的保护环结构。 保护环结构包括在器件形成区域和划线区域之间传送电信号的信号传输元件。

公开(公告)号：US08045400B2

公开(公告)日：2011-10-25

申请号：US12495269

申请日：2009-06-30

申请人： Je-Yoon Kim ,  Jong-Chern Lee

发明人： Je-Yoon Kim ,  Jong-Chern Lee

IPC分类号： G11C7/00

CPC分类号： G11C19/00

摘要： A circuit for controlling the read cycle includes plurality of shift stages configured to sequentially shift read signals; and an activating unit configured to activate a read cycle signal which represents a read cycle, by performing logical operation for output signals of the plurality of the shift stages, wherein the plurality of the shift stages are configured to sequentially shift the read signals for a period corresponding to burst setting information.

摘要翻译： 用于控制读周期的电路包括被配置为依次移位读信号的多个移位级; 以及激活单元，被配置为通过对所述多个移位级的输出信号执行逻辑运算来激活表示读取周期的读取周期信号，其中所述多个移位级被配置为将所读取的信号顺序地移位一段时间 对应于突发设置信息。

公开(公告)号：US20110102065A1

公开(公告)日：2011-05-05

申请号：US12650501

申请日：2009-12-30

申请人： Sin Hyun JIN ,  Jong Chern Lee

发明人： Sin Hyun JIN ,  Jong Chern Lee

IPC分类号： H03H11/40

CPC分类号： H01L24/49 ,  G11C5/04 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor apparatus having a plurality of stacked chips includes: a plurality of latch units, each of which is disposed in a corresponding one of the plurality of chips and is configured to latch a clock signal and a frequency-divided signal at mutually different points of time to generate an chip identification signal of the corresponding one of the plurality of chips; and a plurality of chip selection signal generating units, each of which is disposed in the corresponding one of the plurality of chips and is configured to compare the chip identification signal of the corresponding one of the plurality of chips with a chip selection identification signal to generate a chip selection signal of the corresponding one of the plurality of chips, wherein the chip selection signal is configured to enable the corresponding one of the plurality of chips when the chip identification signal matches the chip selection identification signal.

摘要翻译： 具有多个堆叠芯片的半导体装置包括：多个锁存单元，每个锁存单元布置在所述多个芯片中的相应一个芯片中，并且被配置为在时钟信号和分频信号的相互不同的点处锁存时钟信号和分频信号 时间来生成多个芯片中的相应一个芯片的芯片识别信号; 以及多个芯片选择信号生成单元，其各自设置在所述多个芯片的对应的一个芯片中，并且被配置为将所述多个芯片中的相应一个芯片的芯片识别信号与芯片选择识别信号进行比较，以生成 所述芯片选择信号被配置为当所述芯片识别信号与所述芯片选择识别信号匹配时，使所述多个芯片中的相应一个芯片能够使能。