公开(公告)号：US09035275B2

公开(公告)日：2015-05-19

申请号：US13330525

申请日：2011-12-19

Applicant: Wei-Chih Chien ,  Ming-Hsiu Lee ,  Shih-Hung Chen

Inventor： Wei-Chih Chien ,  Ming-Hsiu Lee ,  Shih-Hung Chen

IPC: H01L29/06 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633

Abstract: A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.

Abstract translation: 一种自对准堆叠式存储单元阵列结构及其制造方法。 存储单元阵列包括与形成在沟槽内的导电线的相对侧相邻设置的一堆存储单元。 存储单元被堆叠，使得每个存储单元的存储元件表面形成导电线的侧壁的一部分。 导电线形成在沟槽内，使得电接触跨越每个存储单元的整个存储元件表面。 用于制造这种结构的这种结构和方法是不需要使用任何附加掩模的自对准过程。

公开(公告)号：US08378382B2

公开(公告)日：2013-02-19

申请号：US11027807

申请日：2004-12-30

Applicant: Chao-I Wu ,  Ming Hsiu Lee

Inventor： Chao-I Wu ,  Ming Hsiu Lee

IPC: H01L29/66 ,  H01L29/861

CPC classification number: H01L27/0814 ,  H01L27/1021 ,  H01L29/8613

Abstract: A semiconductor device having high-aspect-ratio PN-junctions is provided. The semiconductor device includes a conducting layer. The semiconductor device further includes a plurality of first doped regions formed over the conducting layer. The sidewalls of the doped regions are doped to form PN-junctions. The semiconductor device also includes a plurality of second doped regions over the first doped regions.

Abstract translation: 提供了具有高纵横比PN结的半导体器件。 半导体器件包括导电层。 半导体器件还包括形成在导电层上的多个第一掺杂区域。 掺杂区域的侧壁被掺杂以形成PN结。 半导体器件还包括在第一掺杂区域上的多个第二掺杂区域。

公开(公告)号：US08363463B2

公开(公告)日：2013-01-29

申请号：US12729837

申请日：2010-03-23

Applicant: Yen-Hao Shih ,  Huai-Yu Cheng ,  Chieh-Fang Chen ,  Chao-I Wu ,  Ming Hsiu Lee ,  Hsiang-Lan Lung ,  Matthew J. Breitwisch ,  Simone Raoux ,  Chung H Lam

Inventor： Yen-Hao Shih ,  Huai-Yu Cheng ,  Chieh-Fang Chen ,  Chao-I Wu ,  Ming Hsiu Lee ,  Hsiang-Lan Lung ,  Matthew J. Breitwisch ,  Simone Raoux ,  Chung H Lam

IPC: G11C11/00

CPC classification number: H01L45/1625 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1641

Abstract: A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.

Abstract translation: 一种具有存储元件的相变存储器件，该存储元件包括诸如硫族化物的基本相变材料和一种或多种添加剂，其中所述添加剂或添加剂沿着穿过存储元件的电极间电流路径具有非恒定浓度分布 。 根据不同的晶体学，热学和电学条件以及不同的相变条件，使用非恒定浓度分布的添加剂可以使用不同的材料和浓度掺杂不同的区域。

公开(公告)号：US20120320669A1

公开(公告)日：2012-12-20

申请号：US13161129

申请日：2011-06-15

Applicant: MING-HSIU LEE ,  CHIEH-FANG CHEN

Inventor： MING-HSIU LEE ,  CHIEH-FANG CHEN

IPC: G11C11/21

CPC classification number: G11C8/08 ,  G11C8/10 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0073

Abstract: A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode.

Abstract translation: 提供存储器件。 存储器件包括存储器阵列; 电连接到存储器阵列的第一电路，并使存储器阵列以第一模式工作; 以及电连接到存储器阵列的第二电路，并且使存储器阵列以第二模式工作。

公开(公告)号：US08324605B2

公开(公告)日：2012-12-04

申请号：US12286874

申请日：2008-10-02

Applicant: Hsiang-Lan Lung ,  Chieh-Fang Chen ,  Yen-Hao Shih ,  Ming-Hsiu Lee ,  Matthew J. Breitwisch ,  Chung Hon Lam ,  Frieder H. Baumann ,  Philip Flaitz ,  Simone Raoux

Inventor： Hsiang-Lan Lung ,  Chieh-Fang Chen ,  Yen-Hao Shih ,  Ming-Hsiu Lee ,  Matthew J. Breitwisch ,  Chung Hon Lam ,  Frieder H. Baumann ,  Philip Flaitz ,  Simone Raoux

IPC: H01L47/00 ,  H01L21/06

CPC classification number: H01L45/1226 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

Abstract: A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.

Abstract translation: 使用氧化硅掺杂的硫族化物材料来描述用于制造存储器件的方法和所得到的器件。 具有接触表面的第一电极; 形成包括与第一电极的接触表面接触的部分的多晶状态的相变记忆材料体以及与相变材料体接触的第二电极。 该方法包括在相变材料体内的有源区内熔化和冷却相变存储材料一次或多次，而不会干扰有源区外的多晶态。 导致活性区域中的氧化硅网格与至少一个硫族化物材料结构域形成。 此外，活性区域外的多晶态的相变材料的晶粒尺寸小，结果更均匀。

公开(公告)号：US20110317480A1

公开(公告)日：2011-12-29

申请号：US12823508

申请日：2010-06-25

Applicant: HSIANG-LAN LUNG ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

Inventor： HSIANG-LAN LUNG ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

IPC: G11C11/00 ,  H01L21/06

CPC classification number: G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.

Abstract translation: 集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。 在对数据集进行编码之后，将集成电路相变存储器安装在基板上。 在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。 第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。 第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

公开(公告)号：US20110080780A1

公开(公告)日：2011-04-07

申请号：US12969526

申请日：2010-12-15

Applicant: MING-HSIU LEE ,  YI CHOU CHEN

Inventor： MING-HSIU LEE ,  YI CHOU CHEN

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0092

Abstract: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.

Abstract translation: 编程相变装置的方法包括选择期望的阈值电压（Vth）并将编程脉冲施加到相变装置中的相变材料。 应用编程脉冲包括向相变材料施加一定量的能量以将该材料的至少一部分驱动在熔化能级以上。 施加到相变材料的能量的一部分被允许消散在熔融能级以下。 控制来自相变材料的能量耗散的形状，直到施加到相变材料的能量小于淬火能量水平，以使相变装置具有期望的Vth。 施加到相变材料的能量的剩余部分被允许消散到环境水平。

公开(公告)号：US20110075475A1

公开(公告)日：2011-03-31

申请号：US12965126

申请日：2010-12-10

Applicant: MING-HSIU LEE

Inventor： MING-HSIU LEE

IPC: G11C11/21

CPC classification number: G11C13/0038 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse.

Abstract translation: 这里描述了用于操作这样的设备的存储器件和方法。 本文描述了一种用于操作包括相变材料并且可编程为包括高电阻状态和较低电阻状态的多个电阻状态的存储单元的方法。 该方法包括将第一偏置装置施加到存储器单元以建立较低电阻状态，第一偏置装置包括第一电压脉冲。 该方法还包括确定存储器单元是处于较低电阻状态，以及如果存储单元不处于较低电阻状态，则向存储单元施加第二偏置布置。 第二偏置装置包括具有大于第一电压脉冲的脉冲高度的第二电压脉冲。

公开(公告)号：US20110069538A1

公开(公告)日：2011-03-24

申请号：US12564904

申请日：2009-09-22

Applicant: Chung H. Lam ,  Ming-Hsiu Lee ,  Thomas Nirschi ,  Bipin Rajendran

Inventor： Chung H. Lam ,  Ming-Hsiu Lee ,  Thomas Nirschi ,  Bipin Rajendran

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/0004 ,  G11C11/5678 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0092

Abstract: A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.

Abstract translation: 相变存储器件及其编程方法。 该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。 该方法包括确定用于相变存储器件的特征化的RESET电流斜率。 该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。 该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。 如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。 在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。

公开(公告)号：US20110049456A1

公开(公告)日：2011-03-03

申请号：US12553784

申请日：2009-09-03

Applicant: HSIANG-LAN LUNG ,  CHIEH-FANG CHEN ,  YEN-HAO SHIH ,  HUAI-YU CHENG ,  ERH-KUN LAI ,  MING HSIU LEE ,  MATTHEW J. BREITWISCH ,  SIMONE RAO ,  CHUNG HON LAM

Inventor： HSIANG-LAN LUNG ,  CHIEH-FANG CHEN ,  YEN-HAO SHIH ,  HUAI-YU CHENG ,  ERH-KUN LAI ,  MING HSIU LEE ,  MATTHEW J. BREITWISCH ,  SIMONE RAO ,  CHUNG HON LAM

IPC: H01L45/00 ,  H01L21/06

CPC classification number: H01L45/1625 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1641

Abstract: A memory device is described using a composite doped phase change material between a first electrode and a second electrode. A memory element of phase change material, such as a chalcogenide, is between the first and second electrodes and has an active region. The phase change material has a first dopant, such as silicon oxide, characterized by tending to segregate from the phase change material on grain boundaries in the active region, and has a second dopant, such as silicon, characterized by causing an increase in recrystallization temperature of, and/or suppressing void formation in, the phase change material in the active region.

Abstract translation: 使用在第一电极和第二电极之间的复合掺杂相变材料来描述存储器件。 相变材料的存储元件，例如硫族化物，位于第一和第二电极之间并且具有有源区。 相变材料具有第一掺杂剂，例如氧化硅，其特征在于倾向于在有源区域中的晶界上与相变材料分离，并且具有第二掺杂剂，例如硅，其特征在于引起再结晶温度的增加 的和/或抑制活性区域中的相变材料中的空隙形成。