公开(公告)号：US06204119B1

公开(公告)日：2001-03-20

申请号：US09312572

申请日：1999-05-14

Applicant: Gerrit Lange ,  Martin Franosch ,  Wolfgang Hönlein ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schäfer ,  Reinhard Stengl ,  Hermann Wendt

Inventor： Gerrit Lange ,  Martin Franosch ,  Wolfgang Hönlein ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schäfer ,  Reinhard Stengl ,  Hermann Wendt

IPC: H01L218242

CPC classification number: H01L28/87 ,  Y10S438/97

Abstract: A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p+/p− silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.

Abstract translation: 集成存储器电路中的电容器的制造方法包括：首先将作为蚀刻停止层的第一导电层和辅助层沉积到载体上。 然后在第一导电层和辅助层的顶部上产生包含第一材料和第二材料的交替层的层序列。 层序列可以具体地具有p + / p-硅层或硅/锗层。 从层序列形成具有要制造的电容器的基极的层结构。 层结构的侧面设置有导电支撑结构。 在层结构内形成一个开口，一直到辅助层，然后除去辅助层和由第二材料制成的层。 由第一材料和支撑结构制成的层的自由表面设置有施加对电极的电容器电介质。

公开(公告)号：US06194765B1

公开(公告)日：2001-02-27

申请号：US09313433

申请日：1999-05-17

Applicant: Hans Reisinger ,  Reinhard Stengl ,  Ulrike Grüning ,  Volker Lehmann ,  Hermann Wendt ,  Josef Willer ,  Martin Franosch ,  Herbert Schäfer

Inventor： Hans Reisinger ,  Reinhard Stengl ,  Ulrike Grüning ,  Volker Lehmann ,  Hermann Wendt ,  Josef Willer ,  Martin Franosch ,  Herbert Schäfer

IPC: H01L2976

CPC classification number: H01L27/11 ,  H01L27/1104 ,  Y10S257/903

Abstract: An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

Abstract translation: 集成电路具有至少一个存储单元，其中存储单元设置在半导体衬底的表面的区域中。 存储单元包含彼此电连接的至少两个反相器。 反相器各自包含具有源极，漏极和沟道的两个互补MOS晶体管，所述互补MOS晶体管的沟道具有不同的导电类型。 根据本发明，集成电路被构造成使得逆变器垂直于半导体衬底的表面设置。 互补MOS晶体管的源极，漏极和沟道由层叠在另一个之上的层构成，并且以互补的MOS晶体管彼此上下的方式设置。 本发明还涉及一种用于制造集成电路的方法。

公开(公告)号：US6140177A

公开(公告)日：2000-10-31

申请号：US242153

申请日：1999-02-09

Applicant: Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Volker Lehmann ,  Hans Reisinger ,  Hermann Wendt

Inventor： Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Volker Lehmann ,  Hans Reisinger ,  Hermann Wendt

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L28/92 ,  Y10S438/947

Abstract: For manufacturing a capacitor that is essentially suited for DRAM arrangements, column structures that form an electrode of the capacitor are etched upon employment of a statistical mask that is produced without lithographic steps by nucleus formation of Si/Ge and subsequent selective epitaxy. Structure sizes below 100 nm can be realized in the statistical mask. Surface enlargement factors up to 60 are thus achieved.

Abstract translation: PCT No.PCT / DE97 / 01408 Sec。 371日期1999年2月9日 102（e）1999年2月9日PCT PCT 1997年7月3日PCT公布。 出版物WO98 / 07184 日期1998年2月19日为了制造基本上适用于DRAM布置的电容器，使用形成电容器电极的列结构被蚀刻，使用统计掩模，其通过Si / Ge的核形成并且随后选择性地产生无平版印刷步骤 外延 在统计掩模中可以实现小于100nm的结构尺寸。 从而达到高达60的表面增大因子。

公开(公告)号：US6127220A

公开(公告)日：2000-10-03

申请号：US312571

申请日：1999-05-14

Applicant: Gerrit Lange ,  Martin Franosch ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schafer ,  Reinhard Stengl ,  Hermann Wendt

Inventor： Gerrit Lange ,  Martin Franosch ,  Volker Lehmann ,  Hans Reisinger ,  Herbert Schafer ,  Reinhard Stengl ,  Hermann Wendt

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: On a carrier a layer sequence is applied which contains alternatingly layers made of a first conducting material and a second material in which both materials are different from a carrier material. An opening is made in the layer sequence, which is filled with a conducting material so that a central supporting structure is produced. Then the layer sequence is structured corresponding to the dimensions of a capacitor and the layers made of the second material are removed selectively, so that a first capacitor electrode is formed. The layer sequence may have especially p.sup.+ -/p.sup.- silicon layers or silicon/germanium layers. An etch-stop layer can also be incorporated as the lowest or second-lowest layer.

Abstract translation: 在载体上施加层序列，其包含由第一导电材料和第二材料制成的交替层，其中两种材料都不同于载体材料。 在层序列中形成开口，其中填充有导电材料，从而产生中心支撑结构。 然后根据电容器的尺寸构造层序列，并且选择性地去除由第二材料制成的层，从而形成第一电容器电极。 层序列可以具有特别的p + - / p-硅层或硅/锗层。 也可以将蚀刻停止层作为最低层或第二层加入。

公开(公告)号：US5945704A

公开(公告)日：1999-08-31

申请号：US105945

申请日：1998-06-26

Applicant: Martin Schrems ,  Jack Mandelman ,  Joachim Hoepfner ,  Herbert Schaefer ,  Reinhard Stengl

Inventor： Martin Schrems ,  Jack Mandelman ,  Joachim Hoepfner ,  Herbert Schaefer ,  Reinhard Stengl

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L31/119 ,  H01L27/76

CPC classification number: H01L27/10861 ,  H01L29/945

Abstract: A trench capacitor with an epi layer in the lower portion of the trench. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the lower portion of the trench to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.

Abstract translation: 具有沟槽下部的外延层的沟槽式电容器。 外延层用作沟槽电容器的掩埋板。 扩散区域围绕沟槽的下部以增强外延层的掺杂剂浓度。 扩散区域通过例如气相掺杂，等离子体掺杂或等离子体浸入离子注入形成。

公开(公告)号：US5943571A

公开(公告)日：1999-08-24

申请号：US883571

申请日：1997-06-26

Applicant: Herbert Schaefer ,  Martin Franosch ,  Reinhard Stengl ,  Volker Lehmann ,  Hans Reisinger ,  Hermann Wendt

Inventor： Herbert Schaefer ,  Martin Franosch ,  Reinhard Stengl ,  Volker Lehmann ,  Hans Reisinger ,  Hermann Wendt

IPC: C23C16/04 ,  H01L21/033 ,  H01L21/20 ,  H01L21/205 ,  H01L21/266 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  C23C16/04 ,  H01L21/02381 ,  H01L21/02425 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0334 ,  H01L27/11517 ,  H01L29/66825

Abstract: For manufacturing fine structures, nuclei that define the dimensions of the fine structures are formed on the surface of a substrate in a CVD process upon employment of a first process gas that contains SiH.sub.4 and GeH.sub.4 in a carrier gas. The nuclei can be employed both as a mask, for example, when etching or implanting, as will as active or passive component parts that remain in the structure, for example, as charge storages in the dielectric of an EEPROM.

Abstract translation: 为了制造精细结构，使用在载气中使用含有SiH 4和GeH 4的第一工艺气体时，在CVD工艺的基板的表面上形成限定精细结构的尺寸的核。 核可以同时用作掩模，例如蚀刻或注入时，以及保留在结构中的有源或无源部件，例如作为电荷存储在EEPROM的电介质中。

公开(公告)号：US5817553A

公开(公告)日：1998-10-06

申请号：US766977

申请日：1996-12-16

Applicant: Reinhard Stengl ,  Martin Franosch ,  Hermann Wendt

Inventor： Reinhard Stengl ,  Martin Franosch ,  Hermann Wendt

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: Capacitors, in particular stacked capacitors for a dynamic memory cell configuration are manufactured by first forming a sequence of layers, which include layers made of a first conductive material alternating with layers made of a second material. The second material can be selectively etched with respect to the first material. Layered structures are formed from the sequence of layers, with the flanks of the layered structures each having a conductive support structure. The layered structures are formed with openings, such as gaps, in which the surface of the layers is exposed. The layers made of the second material are selectively removed with respect to the layers made of the first material. The exposed surface of the layers made of the first material and of the support structure are provided with a capacitor dielectric, onto which a counter-electrode is placed. The capacitor is made by etching p.sup.- -doped polysilicon that is selective to p.sup.+ -doped polysilicon.

Abstract translation: 制造用于动态存储单元配置的电容器，特别是用于动态存储单元配置的层叠电容器，是通过首先形成一层层而制成的，该层包括由与第二材料制成的层交替的第一导电材料制成的层。 可以相对于第一材料选择性地蚀刻第二材料。 层状结构由层序列形成，层状结构的侧面各自具有导电支撑结构。 层状结构形成有诸如间隙的开口，其中层的表面暴露在其中。 由第二材料制成的层相对于由第一材料制成的层选择性地去除。 由第一材料和支撑结构制成的层的暴露表面设置有电容器电介质，其上放置有相对电极。 电容器是通过蚀刻对p +掺杂多晶硅有选择性的p掺杂多晶硅制成的。

公开(公告)号：US5326718A

公开(公告)日：1994-07-05

申请号：US950068

申请日：1992-09-23

Applicant: Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

Inventor： Helmut Klose ,  Thomas Meister ,  Hans-Willi Meul ,  Reinhard Stengl

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/331 ,  H01L21/336 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78

CPC classification number: H01L29/66287 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66651 ,  Y10S148/011

Abstract: A method for the manufacture of a laterally limited single crystal region that is suitable for use as an active part of a transistor.

Abstract translation: 一种用于制造适合用作晶体管的有源部分的横向受限的单晶区域的方法。