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    Voltage slope control method and apparatus for power driver circuit application
    61.
    发明授权
    Voltage slope control method and apparatus for power driver circuit application 有权
    电力斜坡控制方法和电源驱动电路应用的装置

    公开(公告)号：US09236854B2

    公开(公告)日：2016-01-12

    申请号：US13888843

    申请日：2013-05-07

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

    Inventor： Meng Wang ,  Tao Tao Huang

    IPC: H05B37/02 ,  H03K5/12

    CPC classification number: H03K5/12

    Abstract: A drive circuit includes a first transistor coupled in series with a second transistor at a first intermediate node coupled to a load. An amplifier has an output driving a control terminal of the second transistor. The amplifier includes a first input coupled to a second intermediate node and a second input coupled to a reference voltage. A feedback circuit is coupled between the first intermediate node and the second intermediate node. A slope control circuit is coupled the second intermediate node. The slope control circuit injects a selected value of current into the second intermediate node, that current operating to control the output of the amplifier in setting a slope for change in voltage at the first intermediate node.

    Abstract translation: 驱动电路包括与耦合到负载的第一中间节点与第二晶体管串联耦合的第一晶体管。 放大器具有驱动第二晶体管的控制端的输出。 放大器包括耦合到第二中间节点的第一输入和耦合到参考电压的第二输入。 反馈电路耦合在第一中间节点和第二中间节点之间。 斜坡控制电路耦合第二中间节点。 斜坡控制电路将选择的电流值注入到第二中间节点中，该电流在设定第一中间节点处电压变化的斜率时控制放大器的输出。

    DRIVER CIRCUIT WITH GATE CLAMP SUPPORTING STRESS TESTING
    62.
    发明申请
    DRIVER CIRCUIT WITH GATE CLAMP SUPPORTING STRESS TESTING 有权
    带门夹的驱动电路支持应力测试

    公开(公告)号：US20150381148A1

    公开(公告)日：2015-12-31

    申请号：US14449232

    申请日：2014-08-01

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

    Inventor： Ni Zeng

    IPC: H03K3/011 ,  H03K17/687

    CPC classification number: H03K5/08 ,  G01R31/2621 ,  H03K3/011 ,  H03K17/08122 ,  H03K17/687

    Abstract: A generator circuit is coupled to apply a control signal the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.

    Abstract translation: 发电机电路被耦合以施加驱动输出节点的功率晶体管的栅极端子的控制信号。 产生参考电压，其具有第一电压值作为控制信号的基准，并具有用于应力测试的第二，较高的电压值。 在参考电压和功率晶体管栅极之间提供钳位电路，以在两种模式下起作用。 在一种模式中，当发电机电路施加控制信号时，钳位电路施加第一钳位电压以钳位功率晶体管的栅极处的电压。 在另一种模式下，钳位电路在栅极压力测试期间施加第二个较高的钳位电压来钳位功率晶体管的栅极。

    CURRENT SLOPE CONTROL METHOD AND APPARTUS FOR POWER DRIVER CIRCUIT APPLICATION
    63.
    发明申请
    CURRENT SLOPE CONTROL METHOD AND APPARTUS FOR POWER DRIVER CIRCUIT APPLICATION 有权
    电流控制方法和电源驱动电路应用

    公开(公告)号：US20150339963A1

    公开(公告)日：2015-11-26

    申请号：US14818924

    申请日：2015-08-05

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Meng Wang ,  Tao Tao Huang

    IPC: G09G3/20 ,  H03K17/687

    CPC classification number: G09G3/3225 ,  G09G3/20 ,  G09G3/3208 ,  G09G3/3648 ,  G09G2300/0842 ,  G09G2310/0259 ,  G09G2310/0291 ,  G09G2320/041 ,  G09G2320/043 ,  G09G2330/02 ,  G09G2330/025 ,  G09G2330/028 ,  H02M3/158 ,  H03K5/12 ,  H03K17/04123 ,  H03K17/687 ,  H03K2217/0063 ,  H03K2217/0072

    Abstract: A low side driver includes a first transistor coupled in series with a second transistor at a low side voltage node for a load. A capacitance is configured to store a voltage and a voltage buffer circuit has an input coupled to receive the voltage stored by the capacitance and an output coupled to drive a control node of the second transistor with the stored voltage. A current source supplies current through a switch to the capacitance and the input of the voltage buffer circuit. The switch is configured to be actuated by an oscillating enable signal so as to cyclically source current from the current source to the capacitance and cause a stepped increase in the stored voltage which is applied by the buffer circuit to the control node of the second transistor.

    Abstract translation: 低侧驱动器包括与用于负载的低侧电压节点与第二晶体管串联耦合的第一晶体管。 电容被配置为存储电压，并且电压缓冲器电路具有耦合以接收由电容存储的电压的输入和耦合以用所存储的电压驱动第二晶体管的控制节点的输出。 电流源通过开关将电流提供给电容和电压缓冲电路的输入。 该开关被配置为由振荡使能信号激励，以便将来自电流源的电流循环地引导到电容，并且使由缓冲电路施加到第二晶体管的控制节点的存储电压发生阶梯式增加。

    CONGRUENT POWER AND TIMING SIGNALS FOR DEVICE
    64.
    发明申请
    CONGRUENT POWER AND TIMING SIGNALS FOR DEVICE 审中-公开
    用于设备的组合电源和时序信号

    公开(公告)号：US20150326139A1

    公开(公告)日：2015-11-12

    申请号：US14747242

    申请日：2015-06-23

    Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO. LTD ,  STMICROELECTRONICS (CHINA) INVESTMENT CO. LTD

    Inventor： HENRY GE ,  WELSIN WANG ,  XING ZHANG

    IPC: H02M7/06

    CPC classification number: H02M7/06 ,  G01R11/40 ,  G01R11/42 ,  H02M7/068 ,  H02M2001/0064

    Abstract: Congruent power and timing signals in a single electronic device. In an embodiment, a circuit may include just one isolation transformer operable to generate a power signal and a timing signal. On the secondary side, two branches may extract both a power signal and a clock signal for use in the circuit on the isolated secondary side. The first branch may be coupled to the transformer and operable to manipulate the signal into a power signal, such as a 5V DC signal. Likewise, the second circuit branch is operable to manipulate the signal into a clock signal, such as a 5 V signal with a frequency of 1 MHz. By extracting both a power supply signal and a clock signal from the same isolation transformer on the secondary side, valuable space may be saved on an integrated circuit device with only having a single winding for a single isolation transformer.

    Abstract translation: 单个电子设备中的一致功率和定时信号。 在一个实施例中，电路可以仅包括一个可操作以产生功率信号和定时信号的隔离变压器。 在次级侧，两个分支可以提取功率信号和时钟信号，以在隔离次级侧的电路中使用。 第一分支可以耦合到变压器并且可操作以将信号操纵成诸如5V DC信号的功率信号。 类似地，第二电路支路可操作以将信号操纵成时钟信号，例如频率为1MHz的5V信号。 通过从次级侧的同一隔离变压器中提取电源信号和时钟信号，可以在集成电路设备上节省有价值的空间，只需要单个隔离变压器的绕组。

    DEVICE AND METHOD FOR REDUCING CLIPPING IN AN AMPLIFIER
    66.
    发明申请
    DEVICE AND METHOD FOR REDUCING CLIPPING IN AN AMPLIFIER 有权
    用于减小放大器中的剪辑的装置和方法

    公开(公告)号：US20150214902A1

    公开(公告)日：2015-07-30

    申请号：US14534727

    申请日：2014-11-06

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Hong Wu Lin

    IPC: H03F1/26 ,  H03F3/183 ,  H03F3/217

    CPC classification number: H03F1/3205 ,  H03F3/185 ,  H03F3/2171 ,  H03F3/2173 ,  H03F2200/03 ,  H03F2200/351 ,  H03F2200/66

    Abstract: Limiting clipping in an amplifier is accomplished in the feedback loop of a class D PWM amplifier that includes an integrator coupled to an input node and configured to generate an integrated input signal such that a comparator may then generate a PWM signal for driving an amplifier output stage based on a comparison to a triangle wave signal. To this end, the amplifier also includes a threshold signal generator for generating high and low voltage thresholds based on the triangle wave signal to be used to engage compensation circuits for limiting the overall amplification. Such compensation circuits may be bipolar junction transistors that are disposed in the feedback loop of the integrator. Thus, the overall bandwidth of the amplifier itself is not affected by adding a limiter circuit aimed at reducing clipping.

    Abstract translation: 在D类PWM放大器的反馈回路中实现限幅放大器的削波，其包括耦合到输入节点并被配置为产生积分输入信号的积分器，使得比较器然后可以产生用于驱动放大器输出级的PWM信号 基于与三角波信号的比较。 为此，放大器还包括一个阈值信号发生器，用于基于三角波信号产生高和低电压阈值，以用于接合用于限制整个放大的补偿电路。 这种补偿电路可以是布置在积分器的反馈回路中的双极结型晶体管。 因此，放大器本身的总体带宽不受增加限制电路的影响，目的是减少削波。

    Driver circuit for driving power transistors
    68.
    发明授权
    Driver circuit for driving power transistors 有权
    用于驱动功率晶体管的驱动电路

    公开(公告)号：US09007101B2

    公开(公告)日：2015-04-14

    申请号：US14073494

    申请日：2013-11-06

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

    Inventor： Ni Zeng

    IPC: H03K3/00 ,  H03K17/00 ,  H03K17/06

    CPC classification number: H03K17/00 ,  H03K17/06 ,  H03K2017/066 ,  H03K2217/0036 ,  H03K2217/0063

    Abstract: A driver circuit for driving a power transistor includes a converter having a first transistor and a second transistor coupled in series between a supply node and a reference node. The converter is configured to receive a first signal and in response thereto generate a second signal for selectively controlling status of the power transistor. The ratio of a first leakage current of the first transistor to a second leakage current of the second transistor is used in the generation of the second signal which is applied to the control terminal of a transistor switch that is selectively actuated to turn off the power transistor.

    Abstract translation: 用于驱动功率晶体管的驱动电路包括具有串联耦合在供电节点和参考节点之间的第一晶体管和第二晶体管的转换器。 转换器被配置为接收第一信号，并响应于此产生用于选择性地控制功率晶体管状态的第二信号。 第一晶体管的第一泄漏电流与第二晶体管的第二漏电流之比用于产生施加到晶体管开关的控制端的第二信号，晶体管开关被选择性地致动以关断功率晶体管 。

    Fully integrated circuit for generating a ramp signal
    70.
    发明授权
    Fully integrated circuit for generating a ramp signal 有权
    用于产生斜坡信号的完全集成电路

    公开(公告)号：US08907705B2

    公开(公告)日：2014-12-09

    申请号：US13648557

    申请日：2012-10-10

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

    Inventor： Tao Tao Huang ,  Meng Wang

    IPC: H03K4/02 ,  H03K4/06

    CPC classification number: H03K4/502

    Abstract: A fully integrated ramp generator circuit includes a first current generator that sources current to first capacitor through a first transistor that is gate controlled by the complement of a periodic signal. The ramping voltage stored on the first capacitor is buffered to an output node as a ramp output signal. A second transistor couples the output node to the first current generator and is gate controlled by the periodic signal. The periodic signal is generated at the output of a flip-flop that receives an input clock signal and reset signal. The reset signal is generated by a comparator circuit operable to compare the voltage on a second capacitor to a reference. The second capacitor is charged by a second current source and discharged by a third transistor that is gate controlled by the periodic signal.

    Abstract translation: 完全集成的斜坡发生器电路包括第一电流发生器，其通过由周期信号的补码门控制的第一晶体管向第一电容器供电。 存储在第一电容器上的斜坡电压作为斜坡输出信号被缓冲到输出节点。 第二晶体管将输出节点耦合到第一电流发生器，并由周期信号进行栅极控制。 周期性信号在接收输入时钟信号和复位信号的触发器的输出端产生。 复位信号由比较器电路产生，比较器电路可操作以将第二电容器上的电压与参考电压进行比较。 第二电容器由第二电流源充电，并由被周期信号门控制的第三晶体管放电。

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