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公开(公告)号：US12033926B2
公开(公告)日：2024-07-09
申请号：US17498328
申请日：2021-10-11
Applicant: STMicroelectronics S.r.l.
Inventor： Federico Giovanni Ziglioli
IPC: H01L23/00 , H01L21/48 , H01L21/768 , H01L23/31 , H01L23/498 , H01L21/60
CPC classification number: H01L23/49816 , H01L21/4853 , H01L21/76894 , H01L23/3135 , H01L23/49861 , H01L24/13 , H01L2021/60112 , H01L2224/13
Abstract: A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package.
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公开(公告)号：US12033663B2
公开(公告)日：2024-07-09
申请号：US18343868
申请日：2023-06-29
Applicant: STMicroelectronics S.r.l.
Inventor： Ezio Galbiati
CPC classification number: G11B21/025 , G11B25/043 , G11B27/36 , G11B2220/2516
Abstract: A circuit includes a set of input nodes configured to be coupled to respective ones of the windings of a spindle motor in a hard disk drive to sense the voltages applied to the windings. A set of output nodes is configured to provide output signals indicative of direction of flow of the currents through the windings. Level shifters are coupled to respective input nodes in the set of input nodes and have level-shifted output nodes configured to provide down-shifted replicas of the voltages at the respective input nodes in the set of input nodes. Flip-flops have inputs coupled to respective ones of the level-shifted output nodes of the level shifters and outputs configured to provide the output signals coupled to respective output nodes.
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63.发明公开公开(公告)号：US20240220777A1
公开(公告)日：2024-07-04
申请号：US18176315
申请日：2023-02-28
Inventor： Francesca GIRARDI , Giuseppe DESOLI , Ruggero SUSELLA , Thomas BOESCH , Paolo Sergio ZAMBOTTI
IPC: G06N3/0464
CPC classification number: G06N3/0464
Abstract: A hardware accelerator includes functional circuits and streaming engines. An interface is coupled to the plurality of streaming engines. The interface, in operation, performs stream cipher operations on data words associated with data streaming requests. The performing of a stream cipher operation on a data word includes generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines and an address associated with the data word, and XORing the generated mask with the data word. The hardware accelerator may include configuration registers to store configuration information indicating a respective security state associated with functional circuits and streaming engine of the hardware accelerator, which may be used to control performance of operations by the hardware accelerator.
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公开(公告)号：US12027964B2
公开(公告)日：2024-07-02
申请号：US18364811
申请日：2023-08-03
Applicant: STMicroelectronics S.r.l.
Inventor： Maurizio Ricci , Marco Sautto , Simone Bellisai , Eleonora Chiaramonte , Luigi Arpini , Davide Betta
CPC classification number: H02M1/008 , H02M1/0025 , H02M3/156 , H02M3/157 , H02M3/158 , H02M1/0003
Abstract: An embodiment circuit comprises first and second output nodes with an inductor arranged therebetween, and first and second switches coupled to opposing ends of the inductor. The switches are switchable between non-conductive and conductive states to control current flow through the inductor and produce first and second output voltages. The current intensity through the inductor is compared with at least one reference value. Switching control circuitry is coupled with the first and second switches, the first and second output nodes, and current sensing circuitry, which is configured to control the switching frequency of the first and second switches as a function of the output voltages and a comparison at the current sensing circuitry. The switching control circuitry is configured to apply FLL-FFWD processing to produce the reference values as a function of a timing signal, targeting maintaining a constant target value for the converter switching frequency.
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65.发明公开公开(公告)号：US20240212751A1
公开(公告)日：2024-06-27
申请号：US18543847
申请日：2023-12-18
Applicant: STMicroelectronics S.r.l.
Inventor： Riccardo ZURLA , Marco PASOTTI , Marcella CARISSIMI , Alessandro CABRINI
CPC classification number: G11C13/004 , G06F17/16 , G11C13/0004 , G11C13/0028 , G11C13/003 , G11C2213/79
Abstract: A word line activation unit of an in-memory computation generates activation signals as a function of an input value. The in-memory computation device includes a memory array with a plurality of memory cells (each storing a computational weight) coupled to a bit line and each to a word line and a digital detector. A cell current flows through each memory cell as a function of the activation signal and the computational weight and a bit line current is generated as a function of a summation of the cell currents. The digital detector performs successive iterations on the bit line current. In each iteration: an integration stage generates an integration signal indicative of a time integral of the bit line current, and resets the integration signal when the integration signal reaches a threshold; and the counter stage updates the output signal in response to the integration signal reaching the threshold.
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Patent Agency Ranking
公开(公告)号：US12021476B2
公开(公告)日：2024-06-25
申请号：US17514832
申请日：2021-10-29
Applicant: STMicroelectronics S.r.l.
Inventor： Enrico Poli , Vincenzo Marano
IPC: H02P7/29
CPC classification number: H02P7/29
Abstract: A method and apparatus for adaptive rectification for preventing current inversion in motor windings are provided. In the method and apparatus, first and second half bridges of a plurality of half bridges are operated to synchronously rectify and permit passage of current, through the windings of the motor, in a first direction. A change of direction of the current from the first direction to a second direction opposite the first direction is detected. In response to detecting that the current changed direction to the second direction, the first and second half bridges of the plurality of half bridges are operated to quasi-synchronously rectify and block passage of the current through the windings in the second direction.
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67.发明公开公开(公告)号：US20240206133A1
公开(公告)日：2024-06-20
申请号：US18395137
申请日：2023-12-22
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Cristiano Gianluca STELLA , Francesco SALAMONE
IPC: H05K7/20 , H01L23/373 , H01L25/07
CPC classification number: H05K7/209 , H01L23/3735 , H01L25/071
Abstract: The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers.
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公开(公告)号：US20240201351A1
公开(公告)日：2024-06-20
申请号：US18532939
申请日：2023-12-07
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Davide RUGGIERO , Rosario SCHIANO LO MORIELLO
IPC: G01S7/52
CPC classification number: G01S7/52025
Abstract: Method to provide a TOF estimate by a TOF device. The method comprises: generating an electric echo signal indicative of an ultrasonic echo signal returned by a target body by the ultrasonic source signal; determining an envelope signal indicative of an envelope of the electric echo signal; generating a first TOF estimate by processing the electric echo signal; determining an envelope signal portion of the envelope signal based on a non-PSOA hyperparameter; and generating a second TOF estimate by processing the envelope signal portion through PSOA, the second TOF estimate having a measurement accuracy value greater than that of the first TOF estimate. PSOA is optimized based on a PSOA hyperparameter set. The non-PSOA hyperparameter and the PSOA hyperparameter set are selected among a plurality of choices based on the first TOF estimate, so as to obtain the second TOF estimate which has greater accuracy than the first TOF estimate.
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公开(公告)号：US20240199408A1
公开(公告)日：2024-06-20
申请号：US18590533
申请日：2024-02-28
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Giorgio ALLEGATO , Lorenzo CORSO , Ilaria GELMI , Carlo VALZASINA
CPC classification number: B81B3/0051 , B81C1/00595 , B81B2201/0235 , B81B2201/0242 , B81C2201/0198
Abstract: A process for manufacturing a MEMS device includes forming a first structural layer of a first thickness on a substrate. First trenches are formed through the first structural layer, and masking regions separated by first openings are formed on the first structural layer. A second structural layer of a second thickness is formed on the first structural layer in direct contact with the first structural layer at the first openings and forms, together with the first structural layer, thick structural regions having a third thickness equal to the sum of the first and the second thicknesses. A plurality of second trenches are formed through the second structural layer, over the masking regions, and third trenches are formed through the first and the second structural layers by removing selective portions of the thick structural regions.
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公开(公告)号：US12015346B2
公开(公告)日：2024-06-18
申请号：US17565674
申请日：2021-12-30
Applicant: STMicroelectronics S.r.l.
Inventor： Andrea Barbieri , Aldo Vidoni , Marco Zamprogno
CPC classification number: H02M3/158 , H02M1/0025 , H02M1/08
Abstract: A DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a diode coupled between the input node and an output node, and an output capacitor coupled between the output node and ground such that an output voltage is formed across the output capacitor. A switch selectively couples the input node to ground in response to a drive signal. Control loop circuitry includes an error amplifier to generate an analog error voltage based upon a comparison of a feedback voltage to a reference voltage, the feedback voltage being indicative of the output voltage, a quantizer to quantize the analog error voltage to produce a digital error signal, and a drive voltage generation circuit to generate the drive signal as having a duty cycle based upon the digital error signal.
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