公开(公告)号：US11145741B2

公开(公告)日：2021-10-12

申请号：US16591371

申请日：2019-10-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis Gauthier ,  Pascal Chevalier

IPC: H01L29/66 ,  H01L21/22 ,  H01L29/06 ,  H01L29/73

Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.

公开(公告)号：US11139303B2

公开(公告)日：2021-10-05

申请号：US17026869

申请日：2020-09-21

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel ,  Quentin Hubert ,  Thomas Cabout

IPC: H01L27/108 ,  H01L29/66 ,  H01L49/02 ,  H01L29/94

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

公开(公告)号：US20210305311A1

公开(公告)日：2021-09-30

申请号：US17199779

申请日：2021-03-12

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois ROY

IPC: H01L27/148 ,  H04N5/372

Abstract: A charge-coupled device includes an array of insulated electrodes vertically penetrating into a semiconductor substrate. The array includes rows of alternated longitudinal and transverse electrodes. Each end of a longitudinal electrode of a row is opposite and separated from a portion of an adjacent transverse electrode of that row. Electric insulation walls extend parallel to one another and to the longitudinal electrodes. The insulation walls penetrate vertically into the substrate deeper than the longitudinal electrodes. At least two adjacent rows of electrodes are arranged between each two successive insulation walls.

公开(公告)号：US20210305309A1

公开(公告)日：2021-09-30

申请号：US17211723

申请日：2021-03-24

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Thierry BERGER ,  Damien JEANJEAN

IPC: H01L27/146

Abstract: The present disclosure relates to a method for manufacturing a pixel that includes depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; performing chemical mechanical planarization up to the insulating layer, a portion of the electrode layer left in place in the opening forming an electrode; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.

公开(公告)号：US20210296129A1

公开(公告)日：2021-09-23

申请号：US17338379

申请日：2021-06-03

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Denis Monnier ,  Olivier Gonnard

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/285

Abstract: A exemplary semiconductor device includes a first gate structure overlying a surface of the semiconductor body, the first gate structure being silicided. A second gate structure overlies the surface of the semiconductor body and not being silicided. An oxide layer overlies the second gate structure and extends toward the first gate structure. A silicon nitride region is laterally spaced from the second gate structure and overlies a portion of the oxide layer between the first gate structure and the second gate structure.

公开(公告)号：US20210280721A1

公开(公告)日：2021-09-09

申请号：US17323545

申请日：2021-05-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael GROS-JEAN ,  Julien FERRAND

IPC: H01L29/78 ,  H01L21/28 ,  H01L27/07 ,  H01L29/51 ,  H01L29/66

Abstract: A method for manufacturing first and second transistors on a semiconductor substrate includes: depositing an interface layer on the semiconductor substrate; depositing a gate insulator layer on the interface layer; depositing a first ferroelectric layer on the gate insulator layer over a first region for the first transistor; depositing a metal gate layer on the gate insulator layer over a second region for the second transistor and on the first ferroelectric layer over the first region for the first transistor; and patterning the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer to form a first gate stack for the first transistor which includes the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer and a second gate stack for the second transistor which includes the metal gate layer, gate insulator layer and interface layer.

公开(公告)号：US20210273082A1

公开(公告)日：2021-09-02

申请号：US17175758

申请日：2021-02-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Edoardo BREZZA ,  A;exos GAUTHIER ,  Fabien DEPRAT ,  Pascal CHEVALIER

IPC: H01L29/737 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/66 ,  H01L29/417

Abstract: A method of making a bipolar transistor includes forming a stack of a first, second, third and fourth insulating layers on a substrate. An opening is formed in the stack to reach the substrate. An epitaxial process forms the collector of the transistor on the substrate and selectively etches an annular opening in the third layer. The intrinsic part of the base is then formed by epitaxy on the collector, with the intrinsic part being separated from the third layer by the annular opening. The junction between the collector and the intrinsic part of the base is surrounded by the second layer. The emitter is formed on the intrinsic part and the third layer is removed. A selective deposition of a semiconductor layer on the second layer and in direct contact with the intrinsic part forms the extrinsic part of the base.

公开(公告)号：US20210257507A1

公开(公告)日：2021-08-19

申请号：US17308651

申请日：2021-05-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Charles BAUDOT ,  Sebastien CREMER ,  Nathalie VULLIET ,  Denis PELLISSIER-TANON

IPC: H01L31/105 ,  H01L31/0232 ,  G02B6/12 ,  H01L31/028

Abstract: A vertical photodiode includes an active area. The contacting pads for the diode terminals are laterally shifted away from the active area so as to not be located above or below the active area. The active area is formed in a layer of semiconductor material by a lower portion of a germanium area that is intrinsic and an upper portion of the germanium area that is doped with a first conductivity type. The vertical photodiode is optically coupled to a waveguide formed in the layer of semiconductor material.

公开(公告)号：US20210242087A1

公开(公告)日：2021-08-05

申请号：US17160598

申请日：2021-01-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean JIMENEZ MARTINEZ

IPC: H01L21/8228 ,  H01L27/082

Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

公开(公告)号：US11043591B2

公开(公告)日：2021-06-22

申请号：US16437067

申请日：2019-06-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Mickael Gros-Jean ,  Julien Ferrand

IPC: H01L29/78 ,  H01L27/07 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

Abstract: A ferroelectric field effect transistor includes a semiconductor substrate, with first and second source/drain regions being formed within the semiconductor substrate and being separated by a channel region. An interface layer is disposed on the channel region. A gate insulator layer is disposed on the interface layer. A ferroelectric layer is disposed on the gate insulator layer.