公开(公告)号：US20080246516A1

公开(公告)日：2008-10-09

申请号：US11696575

申请日：2007-04-04

Applicant: Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

Inventor： Tim Tri Hoang ,  Sergey Shumarayev ,  Wanli Chang

IPC: H03D13/00

CPC classification number: H03D13/004

Abstract: A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector.

Abstract translation: 相位频率检测器将参考时钟信号与反馈时钟信号进行比较，以在一个或多个输出信号中产生脉冲。 一个或多个输出信号具有最小的脉冲宽度。 相位频率检测器具有温度检测电路。 相位频率检测器使用温度检测电路调节一个或多个输出信号的最小脉冲宽度，以补偿相位频率检测器的温度变化。

公开(公告)号：US07411464B1

公开(公告)日：2008-08-12

申请号：US11430469

申请日：2006-05-08

Applicant: Tim T Hoang ,  Sergey Shumarayev

Inventor： Tim T Hoang ,  Sergey Shumarayev

IPC: H03B5/24 ,  H03L1/00 ,  H03L7/099

CPC classification number: H03K5/1565 ,  H03K3/0315 ,  H03L7/18

Abstract: An oscillator circuit can generate a periodic signal, and a frequency adjustment circuit can adjust the frequency of the periodic signal. The periodic signal may include phase jitter. In one aspect of the invention, the phase jitter may be mitigated by connecting other circuitry to the oscillator circuit and allowing the other circuitry to draw current. In one embodiment, the other circuitry is connected in parallel with the oscillator circuit. In one embodiment, the other circuitry is configured to draw greater current to mitigate more phase jitter and to draw less current to mitigate less phase jitter. In one embodiment, a greater portion of the other circuitry is connected to the oscillator circuit for higher frequencies and a lesser portion of the other circuitry is connected to the oscillator circuit for lower frequencies.

Abstract translation: 振荡器电路可以产生周期信号，并且频率调节电路可以调节周期信号的频率。 周期信号可能包括相位抖动。 在本发明的一个方面，通过将其它电路连接到振荡器电路并允许其它电路抽取电流可以减轻相位抖动。 在一个实施例中，另一个电路与振荡器电路并联连接。 在一个实施例中，另一个电路被配置为绘制更大的电流以减轻更多的相位抖动并绘制更少的电流以减轻较少的相位抖动。 在一个实施例中，其他电路的较大部分连接到振荡器电路用于较高频率，而另一电路的较小部分连接到用于较低频率的振荡器电路。

公开(公告)号：US07355462B1

公开(公告)日：2008-04-08

申请号：US11456484

申请日：2006-07-10

Applicant: Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev

Inventor： Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev

IPC: H03L7/06

CPC classification number: H03L7/089 ,  H03L7/093 ,  H03L7/18

Abstract: A digital controller for a voltage controlled oscillator (VCO) is provided within a phase lock loop (PLL). The digital controller includes a digital filter having first and second inputs for receiving upward and downward adjustment signals, respectively. The digital filter generates an increment signal and a decrement signal in response to the upward and downward adjustment signals, respectively. The digital controller includes a digital counter having first and second inputs for receiving the increment and decrement signals, respectively. The digital counter generates a multi-bit output signal that represents a running sum of the increment and decrement signals. The digital controller further includes a digital-to-analog converter (DAC) having an input for receiving the running sum output signal generated by the digital counter. The DAC is defined to generate a control voltage for the VCO in response to receipt of the running sum output signal from the digital counter.

Abstract translation: 在锁相环（PLL）内提供压控振荡器（VCO）的数字控制器。 数字控制器包括具有分别用于接收上下调节信号的第一和第二输入的数字滤波器。 数字滤波器分别响应于上下调节信号产生增量信号和减量信号。 数字控制器包括一个数字计数器，它具有分别用于接收增量和减量信号的第一和第二输入端。 数字计数器产生一个多位输出信号，表示增量和减量信号的运行和。 数字控制器还包括具有用于接收由数字计数器产生的运行和输出信号的输入的数模转换器（DAC）。 DAC被定义为响应于来自数字计数器的运行和输出信号的接收而产生用于VCO的控制电压。

公开(公告)号：US20070127616A1

公开(公告)日：2007-06-07

申请号：US11292565

申请日：2005-12-02

Applicant: Sergey Shumarayev ,  Rakesh Patel

Inventor： Sergey Shumarayev ,  Rakesh Patel

IPC: H03D3/24

CPC classification number: H03K19/17744 ,  H03L7/0995

Abstract: A field-programmable gate array (“FPGA”) may include data receiver and/or transmitter circuitry that is adapted to receive and/or transmit data at any frequency(ies) or data rate(s) in a wide range of possible frequencies or data rates. Phase-locked loop (PLL) circuitry may be needed for operation of such receiver and/or transmitter circuitry. For satisfactory operation over the wide frequency range, multiple PLL circuits are provided. One of these PLL circuits may be capable of operating over the entire frequency range, possibly with better jitter performance in some portions of the range than in other portions of the range. One or more other PLL circuits may be provided that are focused on particular parts of the broad range, especially where the jitter performance of the first-mentioned PLL may not be adequate to meet some possible needs.

Abstract translation: 现场可编程门阵列（“FPGA”）可以包括数据接收器和/或发射机电路，其适于在宽范围的可能频率中以任何频率或数据速率接收和/或发射数据，或 数据速率。 可能需要锁相环（PLL）电路来操作这种接收器和/或发射器电路。 为了在宽频率范围内的令人满意的操作，提供了多个PLL电路。 这些PLL电路中的一个可能能够在整个频率范围内运行，可能在该范围的某些部分中具有比该范围的其他部分更好的抖动性能。 可以提供一个或多个其他PLL电路，其集中在宽范围的特定部分上，特别是在首先提到的PLL的抖动性能可能不足以满足一些可能需要的地方。

公开(公告)号：US20070030184A1

公开(公告)日：2007-02-08

申请号：US11364589

申请日：2006-02-27

Applicant: Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

Inventor： Toan Thanh Nguyen ,  Thungoc Tran ,  Sergey Shumarayev ,  Arch Zaliznyak ,  Shoujun Wang ,  Ramanand Venkata ,  Chong Lee

IPC: H03M9/00

CPC classification number: H03K19/00 ,  H03K19/17744 ,  H03M9/00 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/033 ,  H04L25/0266

Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).

Abstract translation: 用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。 电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。 该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

公开(公告)号：US20070025436A1

公开(公告)日：2007-02-01

申请号：US11192539

申请日：2005-07-28

Applicant: Sergey Shumarayev ,  Wilson Wong ,  Rakesh Patel

Inventor： Sergey Shumarayev ,  Wilson Wong ,  Rakesh Patel

IPC: H03H7/30

CPC classification number: H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03573

Abstract: Equalization circuitry for receiving a digital data signal includes both feed-forward equalizer (“FFE”) circuitry and decision-feedback equalizer (“DFE”) circuitry. The FFE circuitry may be used to give the DFE circuitry a signal that is at least minimally adequate for proper start-up of the DFE circuitry. Thereafter, more of the burden of the equalization task may be shifted from the FFE circuitry to the DFE circuitry.

Abstract translation: 用于接收数字数据信号的均衡电路包括前馈均衡器（“FFE”）电路和判决反馈均衡器（“DFE”）电路。 FFE电路可以用于给DFE电路提供至少最不足以适当启动DFE电路的信号。 此后，均衡任务的更多负担可能从FFE电路转移到DFE电路。

公开(公告)号：US20070018863A1

公开(公告)日：2007-01-25

申请号：US11270718

申请日：2005-11-08

Applicant: Tim Hoang ,  Sergey Shumarayev

Inventor： Tim Hoang ,  Sergey Shumarayev

IPC: H03M9/00

CPC classification number: G06F1/10 ,  H03K19/177 ,  H03K19/17736

Abstract: Circuitry for distributing clock signals (e.g., reference clock signals) among a plurality of blocks of circuitry. Each block may include reference clock source circuitry and reference clock utilization circuitry. Each block also preferably includes an identical or substantially identical module of clock signal distribution circuitry that can (1) accept a signal from the source circuitry in that block, (2) apply any of several clock signals to the utilization circuitry in that block, and (3) connect to the similar module(s) of one or more adjacent blocks.

Abstract translation: 用于在多个电路块之间分配时钟信号（例如，参考时钟信号）的电路。 每个块可以包括参考时钟源电路和参考时钟利用电路。 每个块还优选地包括相同或基本相同的时钟信号分配电路模块，其可以（1）接收来自该块中的源电路的信号，（2）将几个时钟信号中的任何一个应用于该块中的利用电路，以及 （3）连接到一个或多个相邻块的相似模块。

公开(公告)号：US07132847B1

公开(公告)日：2006-11-07

申请号：US10708303

申请日：2004-02-24

Applicant: Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

Inventor： Wilson Wong ,  Sergey Shumarayev ,  Rakesh Patel

IPC: H03K19/003

CPC classification number: H03K17/6872 ,  H03K17/164

Abstract: A programmable technique is used to control the slew rate of a differential output buffer. A method controls the slew rate (SR) by changing an “on” resistance of the switches used to steer the current. This can be accomplished by (i) using different size switches or (ii) changing the slew rate of the predrivers which drive the final switches. The latter approach has the advantage that it only temporarily increases the “on” resistance, which does not cause any headroom problems after the transient. A specific application is for the differential outputs of a programmable logic integrated circuits.

Abstract translation: 可编程技术用于控制差分输出缓冲器的转换速率。 一种方法通过改变用于转向电流的开关的“导通”电阻来控制转换速率（SR）。 这可以通过（i）使用不同尺寸的开关或（ii）改变驱动最终开关的预驱动器的转换速率来实现。 后一种方法的优点在于它仅暂时增加了“接通”电阻，这在瞬时之后不会引起任何余量问题。 具体应用是可编程逻辑集成电路的差分输出。

公开(公告)号：US07109744B1

公开(公告)日：2006-09-19

申请号：US11226710

申请日：2005-09-13

Applicant: Sergey Shumarayev ,  Thomas White

Inventor： Sergey Shumarayev ,  Thomas White

IPC: H03K19/0175

CPC classification number: H04L25/0298

Abstract: Various embodiments for implementing circuits and systems with highly flexible interface circuitry that is capable of realizing programmable on-chip termination and DC level control. A number of techniques use existing I/O resources to implement programmable on-chip termination and DC level control that enable an integrated circuit to meet a variety of different high speed single-ended and differential I/O standards.

Abstract translation: 用于实现具有高度灵活的接口电路的电路和系统的各种实施例，其能够实现可编程的片上终止和DC电平控制。 许多技术使用现有的I / O资源实现可编程片上终止和DC电平控制，使集成电路能够满足各种不同的高速单端和差分I / O标准。

公开(公告)号：US06888370B1

公开(公告)日：2005-05-03

申请号：US10645932

申请日：2003-08-20

Applicant: Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

Inventor： Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

IPC: H03K19/0175 ,  H04L25/02

CPC classification number: H04L25/0278

Abstract: The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.

Abstract translation: 片内阻抗终端电路可以动态调节，以匹配传输线阻抗值。 集成电路上的终端电阻网络为耦合到IO引脚的传输线提供终端阻抗。 终端电阻器串联耦合并且彼此并联。 通孔与电阻耦合。 传递门单独接通或断开以将电阻与传输线耦合或去耦。 每个通过门被设置为ON或OFF以向传输线提供所选择的终端电阻值。 可以增加或减少电阻网络的终端电阻以匹配不同传输线路的阻抗。 也可以改变终端电阻以补偿由集成电路上的温度变化或其他因素引起的电阻器的变化。