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    Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test
    61.
    发明授权
    Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test 有权
    使用位线预充电应力操作来对存储单元进行测试的硅绝缘体SRAM存储单元的稳定性测试

    公开(公告)号：US06643804B1

    公开(公告)日：2003-11-04

    申请号：US09552410

    申请日：2000-04-19

    申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Douglas Michael Dewanz

    发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Douglas Michael Dewanz

    IPC分类号： G11C2900

    CPC分类号： G11C29/12 ,  G11C11/41 ,  G11C2029/1204

    摘要： An apparatus, program product, and method of testing a silicon-on-insulator (SOI) static random access memory (SRAM) introduce switching history effects to a memory cell during testing to stress the memory cell such that a reliable determination of stability may be made. Stress is applied to a memory cell through the use of a bitline precharge stress operation, which utilizes the bitline pairs coupled to a memory cell to attempt to flood the memory cell with charge and thereby attempt to cause the memory cell to unexpectedly switch state. The bitline precharge stress operation is performed immediately after the memory cell has been switched to one state after being maintained in an opposite state for a length of time that is sufficient to introduce switching history effects to the memory cell. While a bitline precharge operation may be implemented separate from any write operation, the bitline precharge stress operation may also be incorporated into a write operation through delaying the deassertion of the wordline that occurs in a conventional write operation until after initiation of the bitline precharge operation that conventionally occurs near the end of such a write operation.

    摘要翻译： 一种测试绝缘体上硅（SOI）静态随机存取存储器（SRAM）的装置，程序产品和方法在测试期间向存储器单元引入开关历史效应以对存储单元施加压力，从而稳定性的可靠确定可以是 制作。 通过使用位线预充电应力操作将应力施加到存储器单元，其利用耦合到存储器单元的位线对尝试以充电方式溢出存储器单元，从而尝试使存储器单元意外地切换状态。 在将存储单元切换到一个状态之后，立即执行位线预充电应力操作，并将其保持在相反的状态，持续足以将切换历史效应引入存储单元的时间长度。 尽管位线预充电操作可以与任何写操作分开实施，但是位线预充电应力操作也可以通过延迟在常规写操作中发生的字线的取消取消而被并入到写操作中，直到在开始位线预充电操作之后， 通常在这种写入操作的结束附近发生。

    Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic
    63.
    发明授权
    Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic 有权
    实现增强的阵列访问时间跟踪，内置动态内存和随机逻辑的自检逻辑

    公开(公告)号：US07925950B2

    公开(公告)日：2011-04-12

    申请号：US12393156

    申请日：2009-02-26

    申请人： Todd Alan Christensen ,  Peter Thomas Freiburger ,  Jesse Daniel Smith

    发明人： Todd Alan Christensen ,  Peter Thomas Freiburger ,  Jesse Daniel Smith

    IPC分类号： G01R31/28

    CPC分类号： G11C29/14 ,  G11C29/50012

    摘要： A method and circuit for implementing substantially perfect array access time tracking with Logic Built In Self Test (LBIST) diagnostics of dynamic memory array and random logic, and a design structure on which the subject circuit resides are provided. The dynamic memory array is initialized to a state for the longest read time for each bit and the dynamic memory array is forced into a read only mode. During LBIST diagnostics with the array in the read only mode, the array outputs are combined with the data inputs to provide random switching data on the array outputs to the random logic.

    摘要翻译： 用于通过动态存储器阵列和随机逻辑的逻辑内置自检（LBIST）诊断以及提供主题电路所在的设计结构来实现基本上完美的阵列访问时间跟踪的方法和电路。 动态存储器阵列被初始化为每个位最长读取时间的状态，并且动态存储器阵列被强制进入只读模式。 在采用只读模式的阵列LBIST诊断期间，阵列输出与数据输入相结合，为阵列输出提供随机逻辑的随机数据。

    Implementing boosted wordline voltage in memories
    64.
    发明授权
    Implementing boosted wordline voltage in memories 有权
    在存储器中实现提升的字线电压

    公开(公告)号：US07924633B2

    公开(公告)日：2011-04-12

    申请号：US12389420

    申请日：2009-02-20

    申请人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Daniel Mark Nelson

    发明人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Daniel Mark Nelson

    IPC分类号： G11C7/00

    CPC分类号： G11C11/413 ,  G11C8/08

    摘要： A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.

    摘要翻译： 一种用于在存储器中实现升压的字线电压的方法和字线电压升压电路，以及设置有该电路所在的设计结构。 字线升压电路接收预充电信号，使用耦合到自举电容器的开关晶体管，并响应于预充电信号产生升压电压电平。 提升的电压电平被施加到字线驱动器的输出级的电压源，导致所选字线的字线电压电平升高。 开关晶体管由预充电信号控制，并且提供升压电压电平的自举电容的节点由开关晶体管驱动为高电平。

    Implementing Enhanced Dual Mode SRAM Performance Screen Ring Oscillator
    65.
    发明申请
    Implementing Enhanced Dual Mode SRAM Performance Screen Ring Oscillator 有权
    实现增强型双模SRAM性能屏幕环形振荡器

    公开(公告)号：US20100188888A1

    公开(公告)日：2010-07-29

    申请号：US12360230

    申请日：2009-01-27

    申请人： Chad Allen Adams ,  Todd Alan Christensen ,  Peter Thomas Freiburger ,  Travis Reynold Hebig

    发明人： Chad Allen Adams ,  Todd Alan Christensen ,  Peter Thomas Freiburger ,  Travis Reynold Hebig

    IPC分类号： G11C11/00

    CPC分类号： G11C11/417 ,  G11C7/1045 ,  G11C8/18 ,  G11C11/412 ,  G11C11/413

    摘要： A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell.

    摘要翻译： 一种用于实现增强型双模式静态随机存取存储器（SRAM）性能屏幕环形振荡器（PSRO）的方法和电路，以及设置有被摄体电路的设计结构。 双模SRAM PSRO包括连接在一起的多个SRAM基块。 多个SRAM基块中的每一个包括八晶体管（8T）SRAM单元，局部评估电路和耦合到SRAM单元的逻辑功能。 八晶体管（8T）静态随机存取存储器（SRAM）单元是未修改的8T SRAM单元。 双模SRAM PSRO包括一种工作模式，其中输出频率由8T SRAM单元的直写性能决定; 和另一种操作模式，其中输出频率由8T SRAM单元的读取性能决定。

    Implementing decoupling capacitors with hot-spot thermal reduction on integrated circuit chips
    68.
    发明授权
    Implementing decoupling capacitors with hot-spot thermal reduction on integrated circuit chips 失效
    在集成电路芯片上实现热点热还原的去耦电容

    公开(公告)号：US07723816B2

    公开(公告)日：2010-05-25

    申请号：US12186837

    申请日：2008-08-06

    申请人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    发明人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    IPC分类号： H01L27/01 ,  H01L31/058

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0805

    摘要： A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.

    摘要翻译： 提供了一种方法和结构，用于在包括绝缘体上硅（SOI）电路的集成电路芯片上实现具有热点热还原的去耦电容器。 绝缘体上硅（SOI）结构包括硅衬底层，由硅衬底层承载的薄掩埋氧化物（BOX）层以及由薄BOX层承载的有源层。 在有源层中的热点区域附近建立导热路径，以减少热效应，包括来自SOI结构背面的背面热连接。 背面热连接包括从SOI结构的背面延伸到硅衬底层中的背面蚀刻开口，形成在所述背面蚀刻开口上的电容器电介质; 以及沉积在填充所述背面蚀刻开口的所述电容器电介质上的热连接材料。

    Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability and Enhanced Area Usage
    70.
    发明申请
    Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability and Enhanced Area Usage 失效
    实现具有增强的SRAM单元稳定性和增强区域使用的Domino读取SRAM的本地评估

    公开(公告)号：US20100046278A1

    公开(公告)日：2010-02-25

    申请号：US12195151

    申请日：2008-08-20

    申请人： Chad Allen Adams ,  Todd Alan Christensen ,  Peter Thomas Freiburger ,  Daniel Mark Nelson

    发明人： Chad Allen Adams ,  Todd Alan Christensen ,  Peter Thomas Freiburger ,  Daniel Mark Nelson

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C11/413

    摘要： A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices.

    摘要翻译： 一种用于实现具有增强的SRAM单元稳定性的多米诺骨牌静态随机存取存储器（SRAM）局部评估的方法和电路，以及提供主题电路所在的设计结构。 实现相关SRAM单元组的读和写操作的SRAM本地评估电路包括真和补补位线，真和补写写数据传播输入，预充电信号和预充电写信号。 相应的预充电装置连接在电压源VDD与真位线和补码位线之间。 第一传递门装置连接在补码位线和真实写入数据传播输入端之间。 第二个通路装置连接在真位线和补码写入数据传播输入之间。 在读取操作期间，预充电写信号禁用通路器件。 在写入操作期间，预充电写入信号使能通路装置。