公开(公告)号：US20120115294A1

公开(公告)日：2012-05-10

申请号：US13349181

申请日：2012-01-12

Applicant: Jong-Won Kim ,  Woon-Kyung Lee

Inventor： Jong-Won Kim ,  Woon-Kyung Lee

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including a cell array region, memory cell transistors disposed at the cell array region, bitlines disposed on the memory cell transistors, and a source plate disposed between the memory cell transistors and the bitlines to veil the memory cell transistors thereunder.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：半导体衬底，包括单元阵列区域，设置在单元阵列区域的存储单元晶体管，设置在存储单元晶体管上的位线;以及设置在存储单元晶体管和位线之间的源极，以对存储单元晶体管 在那里

公开(公告)号：US08119460B2

公开(公告)日：2012-02-21

申请号：US13240575

申请日：2011-09-22

Applicant: Jin-Sung Lee ,  Woon-Kyung Lee

Inventor： Jin-Sung Lee ,  Woon-Kyung Lee

IPC: H01L21/332

CPC classification number: H01L27/11521 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573

Abstract: A semiconductor device includes a plurality of transistors disposed on a semiconductor substrate, a device isolation layer disposed around the transistors, a guard ring disposed to surround the device isolation layer and the transistors, and a guard region disposed between adjacent transistors.

Abstract translation: 半导体器件包括设置在半导体衬底上的多个晶体管，围绕晶体管设置的器件隔离层，设置成围绕器件隔离层和晶体管的保护环以及设置在相邻晶体管之间的保护区。

公开(公告)号：US08116111B2

公开(公告)日：2012-02-14

申请号：US12437209

申请日：2009-05-07

Applicant: Jong-Won Kim ,  Woon-Kyung Lee

Inventor： Jong-Won Kim ,  Woon-Kyung Lee

IPC: G11C5/06

CPC classification number: H01L27/11568 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate including a cell array region, memory cell transistors disposed at the cell array region, bitlines disposed on the memory cell transistors, and a source plate disposed between the memory cell transistors and the bitlines to veil the memory cell transistors thereunder.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：半导体衬底，包括单元阵列区域，设置在单元阵列区域的存储单元晶体管，设置在存储单元晶体管上的位线;以及设置在存储单元晶体管和位线之间的源极，以对存储单元晶体管 在那里

公开(公告)号：US07589374B2

公开(公告)日：2009-09-15

申请号：US11699990

申请日：2007-01-31

Applicant: Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

Inventor： Jai-Hyuk Song ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee

IPC: H01L29/788

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11541

Abstract: Embodiments of the invention provide a semiconductor device and a related method of fabricating a semiconductor device. In one embodiment, the invention provides a semiconductor device comprising a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor substrate, wherein the upper silicon pattern has the same crystal structure as the lower silicon pattern and the active region is defined by a device isolation layer. The semiconductor device further comprises a gate insulating layer disposed between the active region and the first gate electrode.

Abstract translation: 本发明的实施例提供一种制造半导体器件的半导体器件和相关方法。 在一个实施例中，本发明提供一种半导体器件，其包括第一栅电极，其包括下硅图案和上硅图案，并设置在半导体衬底的有源区上，其中上硅图案具有与下硅相同的晶体结构 图案和有源区域由器件隔离层定义。 半导体器件还包括设置在有源区和第一栅电极之间的栅极绝缘层。

公开(公告)号：US07494871B2

公开(公告)日：2009-02-24

申请号：US11647671

申请日：2006-12-29

Applicant: Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

Inventor： Chang-Sub Lee ,  Jeong-Hyuk Choi ,  Woon-Kyung Lee ,  Jai-Hyuk Song ,  Dong-Yean Oh

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.

Abstract translation: 半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。 绝缘层覆盖选择晶体管和单元晶体管。 位线在绝缘层中并且电连接到相应的选择晶体管。 沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。

公开(公告)号：US07388249B2

公开(公告)日：2008-06-17

申请号：US11434128

申请日：2006-05-16

Applicant: Woon-Kyung Lee

Inventor： Woon-Kyung Lee

IPC: H01L29/76

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/11568

Abstract: The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

Abstract translation: 本发明提供一种其中栅极与器件隔离膜自对准的半导体器件及其制造方法。 限制有源区的器件隔离膜设置在半导体衬底的一部分上，并且字线跨过器件隔离膜。 栅极图案设置在字线和有源区之间，并且隧道氧化膜设置在栅极图案和有源区之间。 栅极图案包括以相应顺序沉积的浮置栅极图案，栅极层间电介质膜图案和控制栅极电极图案，并且具有与器件隔离膜自对准的侧壁。 为了形成具有与器件隔离膜自对准的侧壁的栅极图案，在半导体衬底上分别形成栅极绝缘膜和栅极材料膜。

公开(公告)号：US20070210370A1

公开(公告)日：2007-09-13

申请号：US11615098

申请日：2006-12-22

Applicant: Woon-Kyung Lee

Inventor： Woon-Kyung Lee

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A nonvolatile memory device includes an active region defined by a device isolation layer in a semiconductor substrate, a word line passing over the active region and a charge storage region defined by a crossing of the active region and the word line and disposed between the active region and the word line. The charge storage region is disposed at an oblique angle with respect to the word line.

Abstract translation: 非易失性存储器件包括由半导体衬底中的器件隔离层限定的有源区，通过有源区的字线和由有源区和字线的交叉限定的电荷存储区，并且设置在有源区 和字线。 电荷存储区域相对于字线倾斜设置。

公开(公告)号：US20070026657A1

公开(公告)日：2007-02-01

申请号：US11481503

申请日：2006-07-06

Applicant: Woon-Kyung Lee

Inventor： Woon-Kyung Lee

IPC: H01L21/44

CPC classification number: H01L21/76897

Abstract: A method of forming a semiconductor device can include forming a plurality of gate structure patterns including gates and first mask patterns stacked on a semiconductor substrate, the gate structure patterns being spaced apart from each other and extending in a first direction, forming a first interlayer insulating layer covering the gate structure patterns, forming a plurality of second mask patterns extending in a second direction crossing the first direction and spaced apart from each other, and etching the first interlayer insulating layer to form a contact hole, self-aligned to the first and second mask patterns, in at least one contact region defined by a neighboring pair of the first mask patterns and a neighboring pair of the second mask patterns. Related devices are also disclosed.

Abstract translation: 形成半导体器件的方法可以包括形成多个栅极结构图案，其包括在半导体衬底上堆叠的栅极和第一掩模图案，栅极结构图案彼此间隔开并沿第一方向延伸，形成第一层间绝缘 覆盖所述栅极结构图案，形成沿与所述第一方向交叉的第二方向延伸并且彼此间隔开的多个第二掩模图案，并且蚀刻所述第一层间绝缘层以形成与所述第一和第二绝缘层自对准的接触孔， 在由相邻对的第一掩模图案定义的至少一个接触区域和相邻的第二掩模图案对中的第二掩模图案。 还公开了相关设备。

公开(公告)号：US6122188A

公开(公告)日：2000-09-19

申请号：US219024

申请日：1998-12-23

Applicant: Eui-Do Kim ,  Woon-Kyung Lee ,  Jeong-Hyouk Choi

Inventor： Eui-Do Kim ,  Woon-Kyung Lee ,  Jeong-Hyouk Choi

IPC: H01L27/112 ,  G11C11/56 ,  H01L21/8246 ,  G11C17/00

CPC classification number: G11C11/5692 ,  H01L27/1126

Abstract: There is provided a non-volatile memory device having a multi-bit cell structure. In the non-volatile memory device, a memory cell array includes a plurality of cells of a first conductivity type which has different threshold voltages and are arranged in a matrix on a semiconductor substrate. A bulk region of a second conductivity type opposite to the first conductivity underlies the memory cell array and receives a predetermined back bias voltage when a cell is driven. The threshold voltage difference between states can be sufficiently widened because a state having a high bulk concentration is highly susceptible to a body effect. Therefore, reduction of masks leads to process simplicity, reduced turnaround time, and improved process margin.

Abstract translation: 提供了具有多位单元结构的非易失性存储器件。 在非易失性存储器件中，存储单元阵列包括具有不同阈值电压并且以矩阵形式布置在半导体衬底上的第一导电类型的多个单元。 与第一导电性相反的第二导电类型的体区域位于存储单元阵列的底部，并且当单元被驱动时接收预定的反向偏置电压。 由于具有高体积浓度的状态对身体效应非常敏感，所以状态之间的阈值电压差可以被充分地加宽。 因此，减少面罩会导致过程简单，缩短周转时间，并改善工艺余量。

公开(公告)号：US5920784A

公开(公告)日：1999-07-06

申请号：US933839

申请日：1997-09-19

Applicant: Woon-kyung Lee

Inventor： Woon-kyung Lee

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8246

CPC classification number: H01L27/11293

Abstract: A method for manufacturing a buried transistor, which includes the steps of forming a field oxide layer in a substrate, the field oxide region having a central portion having a greater thickness than opposite edge portions thereof, forming source/drain regions in the substrate, on opposite sides of the field oxide layer, removing the field oxide layer, and forming a gate electrode on the resultant structure.

Abstract translation: 一种埋入晶体管的制造方法，包括以下步骤：在衬底中形成场氧化物层，所述场氧化物区域具有比其相对边缘部分厚的中心部分，在衬底中形成源/漏区，在 场氧化物层的相对侧，去除场氧化物层，并在所得结构上形成栅电极。