公开(公告)号：US06552950B2

公开(公告)日：2003-04-22

申请号：US09996240

申请日：2001-11-28

Applicant: Tae-Hee Cho ,  Yeong-Taek Lee

Inventor： Tae-Hee Cho ,  Yeong-Taek Lee

IPC: G11C800

CPC classification number: G11C16/08

Abstract: A nonvolatile semiconductor memory device comprising a main memory cell array and a spare memory cell array, capable of freely accessing data in the spare memory cell array irrespective of the physical addresses of the spare memory cell array, and a method thereof are disclosed. The logical addresses of the spare memory cell array are assigned prior to the logical addresses of the main memory cell array in response to a first control signal, and data stored in the spare memory cell array is read earlier than data in the main memory cell array.

公开(公告)号：US06483744B2

公开(公告)日：2002-11-19

申请号：US09887904

申请日：2001-06-21

Applicant: Eun-Cheol Kim ,  Yeong-Taek Lee

Inventor： Eun-Cheol Kim ,  Yeong-Taek Lee

IPC: G11C1604

CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/24

Abstract: A non-volatile semiconductor memory device including a memory cell array having a plurality of memory cells coupled to a plurality of bitlines and wordlines, each memory cell being programmed to one of plurality of data storage states. A node is connected to a selected bitline responsive to a storage state in a selected memory cell. A plurality of latched registers is connected to the node to store and output data bits corresponding the storage state, the data bits being assigned to the selected bitline. A circuit is adapted to precharge the selected bitline before sensing the selected memory cell and is adapted to equalize the selected bitline and the node after sensing the selected memory cell.

Abstract translation: 一种非易失性半导体存储器件，包括具有耦合到多个位线和字线的多个存储器单元的存储单元阵列，每个存储器单元被编程为多个数据存储状态之一。 响应于所选存储器单元中的存储状态，节点连接到选定的位线。 多个锁存寄存器连接到节点以存储和输出与存储状态相对应的数据位，数据位被分配给所选择的位线。 电路适于在感测所选择的存储器单元之前对所选位线进行预充电，并且适于在感测所选择的存储器单元之后均衡所选择的位线和节点。

公开(公告)号：US09001560B2

公开(公告)日：2015-04-07

申请号：US14100183

申请日：2013-12-09

Applicant: Sung-Yeon Lee ,  Yeong-Taek Lee ,  Bo-Geun Kim

Inventor： Sung-Yeon Lee ,  Yeong-Taek Lee ,  Bo-Geun Kim

IPC: G11C13/00 ,  G11C16/10 ,  G11C7/00 ,  G11C11/56 ,  G11C7/10

CPC classification number: G11C13/0002 ,  G11C7/00 ,  G11C7/1096 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/72

Abstract: Driving methods of a nonvolatile memory device are provided. The driving method includes providing a start pulse adjusted based on a previous write operation to a resistive memory cell to write data, verifying whether the data has accurately been written using the start pulse, and executing a write operation on the resistive memory cell by an incremental one-way write method or a decremental one-way write method according to the verify result. Related nonvolatile memory devices are also provided.

Abstract translation: 提供了非易失性存储器件的驱动方法。 该驱动方法包括：将基于先前写入操作调整的起始脉冲提供给电阻式存储单元以写入数据，使用起始脉冲验证数据是否被准确写入，并且通过增量执行对电阻式存储器单元的写入操作 根据验证结果，单向写入方法或递减单向写入方法。 还提供了相关的非易失性存储器件。

公开(公告)号：US08223529B2

公开(公告)日：2012-07-17

申请号：US12703354

申请日：2010-02-10

Applicant: Ho-Jung Kim ,  Yeong-Taek Lee ,  Chul-Woo Park ,  Sang-Beom Kang

Inventor： Ho-Jung Kim ,  Yeong-Taek Lee ,  Chul-Woo Park ,  Sang-Beom Kang

IPC: G11C11/00

CPC classification number: G11C13/004 ,  G11C8/10 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/005 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/009

Abstract: A resistive memory device includes a resistive memory cell array, an output circuit and an input circuit. The resistive memory cell array includes a plurality of memory cells that are coupled to bitlines. The output circuit generates a sensing output signal during a write operation by sensing a bitline voltage, and generates output data during a read operation by sensing the bitline voltage. The input circuit controls the bitline voltage based on input data for the write operation, and limits the bitline voltage in response to the sensing output signal during the write operation. The memory cells are protected by effectually limiting bitline voltage.

Abstract translation: 电阻式存储器件包括电阻存储单元阵列，输出电路和输入电路。 电阻存储单元阵列包括耦合到位线的多个存储单元。 输出电路通过感测位线电压在写入操作期间产生感测输出信号，并通过感测位线电压在读取操作期间产生输出数据。 输入电路基于用于写入操作的输入数据来控制位线电压，并且在写入操作期间响应于感测输出信号来限制位线电压。 存储单元受到有效限制位线电压的保护。

公开(公告)号：US08014221B2

公开(公告)日：2011-09-06

申请号：US11546403

申请日：2006-10-12

Applicant: Yeong-Taek Lee

Inventor： Yeong-Taek Lee

IPC: G11C7/00

CPC classification number: G11C11/404 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4091 ,  G11C2211/4016

Abstract: A semiconductor memory device includes a memory cell array which includes a plurality of unit memory cells, where each of the unit memory cells comprises complementary first and second floating body transistor capacitor-less memory cells. A logic value written into and read from each unit memory cell is defined by a difference in threshold voltage states of the first and second floating body transistor capacitorless memory cells.

Abstract translation: 半导体存储器件包括存储单元阵列，其包括多个单元存储单元，其中每个单元存储单元包括互补的第一和第二浮体晶体管无电容器存储单元。 写入和读取每个单元存储单元的逻辑值由第一和第二浮体晶体管无电容器存储单元的阈值电压状态的差定义。

公开(公告)号：US07843733B2

公开(公告)日：2010-11-30

申请号：US12136933

申请日：2008-06-11

Applicant: Doo-gon Kim ,  Ki-tae Park ,  Yeong-taek Lee

Inventor： Doo-gon Kim ,  Ki-tae Park ,  Yeong-taek Lee

IPC: G11C16/04

CPC classification number: G11C16/3418

Abstract: Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.

Abstract translation: 提供闪存器件，其包括垂直堆叠的多个层。 多个层中的每一个包括多个存储单元。 行解码器电耦合到多个层并且被配置为向多个层提供字线电压。 提供在多个层中的至少两层中的存储单元属于相同的存储块，并且与多个层中的至少两个层中的存储单元相关联的字线电耦合。

公开(公告)号：US07835191B2

公开(公告)日：2010-11-16

申请号：US12292242

申请日：2008-11-14

Applicant: Yeong-Taek Lee

Inventor： Yeong-Taek Lee

IPC: G11C16/06

CPC classification number: G11C16/10 ,  G11C16/24 ,  G11C16/30

Abstract: A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging bit lines. The EEPROM has a PMOS pull-up transistor and an NMOS pull down transistor connected to a virtual power node. A control circuit for charging or discharging bit lines controls the gate voltage of the PMOS or NMOS transistor to limit peak current when charging or discharging bit lines via the virtual power node. In particular, the control circuit operates the PMOS or NMOS transistor in a non-saturation mode to limit current. One such control circuit creates a current mirror or applies a reference voltage to control gate voltages. A programming method sets up bit lines by pre-charging unselected bit lines via the PMOS pull-up transistor having controlled gate voltage while latches in the programming circuitry charge or discharge selected bit lines according to respective data bits being stored. Another bit line setup includes two stages. A first stage pre-charges all bit lines via PMOS pull-up, and the second stage uses the latches to discharge or leave charged the selected bit lines depending on respective data bits being stored. The gate voltages of NMOS transistors in the programming circuitry can be controlled to reduce noise caused by discharging selected bit lines through the latches.

Abstract translation: 具有屏蔽位线结构的NAND EEPROM降低了由于充电或放电位线而导致的电源电压和接地噪声。 EEPROM具有连接到虚拟电源节点的PMOS上拉晶体管和NMOS下拉晶体管。 用于对位线进行充电或放电的控制电路控制PMOS或NMOS晶体管的栅极电压，以便通过虚拟电源节点对位线充电或放电时限制峰值电流。 特别地，控制电路以非饱和模式操作PMOS或NMOS晶体管以限制电流。 一个这样的控制电路产生电流镜或施加参考电压来控制栅极电压。 编程方法通过经由具有受控栅极电压的PMOS上拉晶体管对未选择的位线进行预充电来建立位线，同时编程电路中的锁存器根据存储的相应数据位对所选择的位线进行充电或放电。 另一个位线设置包括两个阶段。 第一级通过PMOS上拉对所有位线进行预充电，第二级根据存储的相应数据位使用锁存器对所选位线进行放电或放电。 可以控制编程电路中的NMOS晶体管的栅极电压，以减少通过锁存器放电所选位线所引起的噪声。

公开(公告)号：US20100265769A1

公开(公告)日：2010-10-21

申请号：US12823726

申请日：2010-06-25

Applicant: SOON WOOK HWANG ,  Ki Tae Park ,  Yeong Taek Lee

Inventor： SOON WOOK HWANG ,  Ki Tae Park ,  Yeong Taek Lee

IPC: G11C16/04

CPC classification number: G11C16/08 ,  G11C7/227 ,  G11C16/0483

Abstract: An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.

Abstract translation: 电可擦除可编程非易失性半导体存储器件。 半导体存储器件包括存储单元阵列，其包括多个存储块，每个存储块包括多个存储器单元，一个虚拟存储单元和一个选择栅极晶体管。 每个具有连接在对应的字线使能信号线和相应的字线之间的电流路径的传输晶体管由块选择电路的输出控制。 转移晶体管包括电耦合到虚拟存储器单元的虚拟转移晶体管，并且被配置为发送伪字线使能信号。

公开(公告)号：US07773444B2

公开(公告)日：2010-08-10

申请号：US11560223

申请日：2006-11-15

Applicant: Yeong-Taek Lee

Inventor： Yeong-Taek Lee

IPC: G11C7/06 ,  G11C7/14

CPC classification number: G11C11/404 ,  G11C11/4091 ,  G11C2211/4016

Abstract: A semiconductor memory device having a first memory cell array block including a memory cell having a floating body, the memory cell coupled to a word line, a first bit line, and a first source line, a second memory cell array block including a reference memory cell having a floating body, the reference memory cell coupled to a reference word line, a second bit line, and a second source line, a first isolation gate portion configured to selectively transmit a signal between the first bit line and at least one of a sense bit line and an inverted sense bit line, a second isolation gate portion configured to selectively transmit a signal between the second bit line and at least one of the sense bit lines, and a sense amplifier configured to amplify voltages of the sense bit line and the inverted sense bit line to first and second sense amplifying voltage levels.

Abstract translation: 一种具有第一存储单元阵列块的半导体存储器件，包括具有浮体的存储单元，耦合到字线的存储单元，第一位线和第一源极线，包括参考存储器的第二存储单元阵列块 具有浮体的单元，耦合到参考字线的参考存储单元，第二位线和第二源极线，第一隔离栅极部分，被配置为选择性地在第一位线和第一位线之间的信号 感测位线和反相感测位线，第二隔离栅极部分，被配置为选择性地在第二位线和感测位线中的至少一个之间传输信号;以及读出放大器，被配置为放大感测位线的电压， 反向感测位线到第一和第二感测放大电压电平。

公开(公告)号：US07755944B2

公开(公告)日：2010-07-13

申请号：US12142460

申请日：2008-06-19

Applicant: Soon-Wook Hwang ,  Ki-Tae Park ,  Yeong-Taek Lee

Inventor： Soon-Wook Hwang ,  Ki-Tae Park ,  Yeong-Taek Lee

IPC: G11C16/04

CPC classification number: G11C16/08 ,  G11C7/227 ,  G11C16/0483

Abstract: An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.

Abstract translation: 电可擦除可编程非易失性半导体存储器件。 半导体存储器件包括存储单元阵列，其包括多个存储块，每个存储块包括多个存储器单元，一个虚拟存储单元和一个选择栅极晶体管。 每个具有连接在对应的字线使能信号线和相应的字线之间的电流路径的传输晶体管由块选择电路的输出控制。 转移晶体管包括电耦合到虚拟存储器单元的虚拟转移晶体管，并且被配置为发送伪字线使能信号。