公开(公告)号：US08389998B2

公开(公告)日：2013-03-05

申请号：US13444768

申请日：2012-04-11

Applicant: Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

Inventor： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

IPC: H01L27/14

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

Abstract: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.

Abstract translation: 根据本发明实施例的薄膜晶体管基板包括：绝缘基板; 形成在所述绝缘基板上的栅极线; 形成在栅极线上的第一层间绝缘层; 形成在所述第一层间绝缘层上的数据线和栅电极; 形成在数据线和栅电极上的栅极绝缘层; 形成在栅极绝缘层上并与栅电极重叠的半导体; 形成在所述半导体上的第二层间绝缘层; 形成在所述第二层间绝缘层上并将所述栅极线和所述栅电极彼此电连接的第一连接; 连接到半导体的漏电极; 连接到所述漏电极的像素电极; 以及将数据线和半导体彼此连接的第二连接。

公开(公告)号：US08289462B2

公开(公告)日：2012-10-16

申请号：US13238788

申请日：2011-09-21

Applicant: Young-Wook Lee ,  Jang-Soo Kim

Inventor： Young-Wook Lee ,  Jang-Soo Kim

IPC: G02F1/136

CPC classification number: H01L27/124 ,  G02F1/136209 ,  G02F1/136286 ,  G02F1/1365 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136222 ,  G02F2001/13629 ,  H01L27/1248

Abstract: A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.

Abstract translation: 薄膜晶体管阵列面板包括基板; 形成在所述基板上的多条栅极线; 与栅极线相交的多条数据线; 连接到栅极线和数据线的多个薄膜晶体管; 形成在栅极线，数据线和薄膜晶体管的上部的多个滤色器; 形成在滤色器上并且包括透明导体的公共电极; 钝化层，其形成在所述公共电极的上部; 以及形成在钝化层的上部并且连接到每个薄膜晶体管的漏电极的多个像素电极。

公开(公告)号：US08111343B2

公开(公告)日：2012-02-07

申请号：US12361511

申请日：2009-01-28

Applicant: Young-Wook Lee ,  Gug-Rae Jo ,  Jang-Soo Kim ,  Jae-Hyoung Youn ,  Byoung-Joo Kim ,  Min-Uk Kim ,  Kyoung-Keun Son

Inventor： Young-Wook Lee ,  Gug-Rae Jo ,  Jang-Soo Kim ,  Jae-Hyoung Youn ,  Byoung-Joo Kim ,  Min-Uk Kim ,  Kyoung-Keun Son

IPC: G02F1/136 ,  G02F1/1335 ,  G02F1/1343

CPC classification number: G02F1/136286 ,  G02F1/133514 ,  G02F2001/136222 ,  G02F2201/40

Abstract: A display substrate includes a plurality of color filters formed on a base substrate, a gate line formed in a trench defined by at least one of the color filters and extended along a first direction, an insulation layer formed on the color filters and the gate line, a data line formed on the insulation layer to be extended along a second direction crossing the first direction, and pixel electrodes formed on the base substrate having the data line formed thereon.

Abstract translation: 显示基板包括形成在基底基板上的多个滤色器，形成在由至少一个滤色器限定的沟槽中并沿着第一方向延伸的沟槽的栅极线，形成在滤色器上的绝缘层和栅极线 形成在沿着与第一方向交叉的第二方向延伸的绝缘层上的数据线以及形成在其上形成有数据线的基底基板上的像素电极。

公开(公告)号：US08045080B2

公开(公告)日：2011-10-25

申请号：US12548897

申请日：2009-08-27

Applicant: Young-Wook Lee ,  Jang-Soo Kim

Inventor： Young-Wook Lee ,  Jang-Soo Kim

IPC: G02F1/136

CPC classification number: H01L27/124 ,  G02F1/136209 ,  G02F1/136286 ,  G02F1/1365 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136222 ,  G02F2001/13629 ,  H01L27/1248

Abstract: A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.

Abstract translation: 薄膜晶体管阵列面板包括基板; 形成在所述基板上的多条栅极线; 与栅极线相交的多条数据线; 连接到栅极线和数据线的多个薄膜晶体管; 形成在栅极线，数据线和薄膜晶体管的上部的多个滤色器; 形成在滤色器上并且包括透明导体的公共电极; 钝化层，其形成在所述公共电极的上部; 以及形成在钝化层的上部并且连接到每个薄膜晶体管的漏电极的多个像素电极。

公开(公告)号：US20110198603A1

公开(公告)日：2011-08-18

申请号：US12902786

申请日：2010-10-12

Applicant: SEUNG-HA CHOI ,  Kyoung-Jae Chung ,  Young-Wook Lee

Inventor： SEUNG-HA CHOI ,  Kyoung-Jae Chung ,  Young-Wook Lee

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/7869 ,  H01L27/1214 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/66969

Abstract: Disclosed are a thin film transistor and a method of forming the thin film transistor.The thin film transistor includes a gate electrode, an oxide semiconductor pattern, a first gate insulating layer pattern interposed between the gate electrode and the oxide semiconductor pattern, wherein the first gate insulating layer pattern has an island shape or has two portions of different thicknesses from each other, a source electrode and a drain electrode electrically connected to the oxide semiconductor pattern, wherein the source electrode and the drain electrode are separated from each other, and a first insulating layer pattern placed between the source electrode and drain electrode and the oxide semiconductor pattern, wherein the first insulating layer pattern partially contacts the source electrode and drain electrode and the first gate insulating layer pattern, and wherein the first insulating layer is enclosed by an outer portion.

Abstract translation: 公开了薄膜晶体管和形成薄膜晶体管的方法。 薄膜晶体管包括栅电极，氧化物半导体图案，插入在栅极电极和氧化物半导体图案之间的第一栅极绝缘层图案，其中第一栅极绝缘层图案具有岛状或具有两个不同厚度的部分 电连接到所述氧化物半导体图案的源电极和漏电极，其中所述源电极和所述漏电极彼此分离;以及第一绝缘层图案，位于所述源电极和漏极之间以及所述氧化物半导体 图案，其中所述第一绝缘层图案部分地接触所述源电极和漏电极以及所述第一栅绝缘层图案，并且其中所述第一绝缘层被外部包围。

公开(公告)号：US20110193076A1

公开(公告)日：2011-08-11

申请号：US12957743

申请日：2010-12-01

Applicant: Pil-Sang YUN ,  Ki-Won KIM ,  Hye-Young RYU ,  Woo-Geun LEE ,  Seung-Ha CHOI ,  Jae-Hyoung YOUN ,  Kyoung-Jae CHUNG ,  Young-Wook LEE ,  Je-Hun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Dong-Ju YANG ,  Young-Joo CHOI

Inventor： Pil-Sang YUN ,  Ki-Won KIM ,  Hye-Young RYU ,  Woo-Geun LEE ,  Seung-Ha CHOI ,  Jae-Hyoung YOUN ,  Kyoung-Jae CHUNG ,  Young-Wook LEE ,  Je-Hun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Dong-Ju YANG ,  Young-Joo CHOI

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract translation: 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US20110159622A1

公开(公告)日：2011-06-30

申请号：US13042348

申请日：2011-03-07

Applicant: Yu-Gwang Jeong ,  Young-Wook Lee ,  Sang-Gab Kim ,  Woo-Geun Lee ,  Min-Seok Oh ,  Jang-Soo Kim ,  Kap-Soo Yoon ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Seung-Hwan Shim ,  Sung-Hoon Yang ,  Ki-Hun Jeong

Inventor： Yu-Gwang Jeong ,  Young-Wook Lee ,  Sang-Gab Kim ,  Woo-Geun Lee ,  Min-Seok Oh ,  Jang-Soo Kim ,  Kap-Soo Yoon ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Seung-Hwan Shim ,  Sung-Hoon Yang ,  Ki-Hun Jeong

IPC: H01L33/62

CPC classification number: H01L27/127 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/66765

Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.

Abstract translation: 本发明的实施例涉及薄膜晶体管和显示面板的制造方法，包括在基板上形成包括栅电极的栅极线，在栅电极上形成栅绝缘层，在栅电极上形成本征半导体 栅极绝缘层，在本征半导体上形成非本征半导体，在外部半导体上形成包括源电极和漏电极的数据线，以及对源电极和漏极之间的非本征半导体的一部分进行等离子体处理，以形成 保护构件和保护构件的相应侧上的欧姆接触。 因此，可以省略用于蚀刻外部半导体和形成用于保护本征半导体的无机绝缘层的工艺，从而可以简化显示面板的制造工艺，可以降低制造成本，并且可以提高生产率。

公开(公告)号：US07926138B2

公开(公告)日：2011-04-19

申请号：US11590918

申请日：2006-11-01

Applicant: Young Wook Lee

Inventor： Young Wook Lee

IPC: D06F37/42

CPC classification number: D06F39/081

Abstract: A laundry treatment apparatus and a controlling method thereof are disclosed. The laundry treatment apparatus includes a leakage detecting device detecting washing water leaking to the lower side of a casing, an auxiliary power supply recharged when a main electric power is supplied, and a controller controlling the auxiliary electric power supply according to the detection by the leakage detecting device. According to the leakage controlling method, since the external electric power inputted to the laundry treatment apparatus is interrupted and the auxiliary power supply is recharged during the supplying of the main electric power to the laundry treatment apparatus when the leakage is detected, an electric leakage and other accidents can be prevented, and an informing device is controlled by the auxiliary power supply so that the leakage can be measured.

Abstract translation: 公开了一种洗衣处理装置及其控制方法。 衣物处理装置包括检测向壳体下侧泄漏的洗涤水的泄漏检测装置，在供给主电力时补充的辅助电源以及根据泄漏的检测来控制辅助电力供给的控制装置 检测装置。 根据泄漏控制方法，由于当检测到泄漏时，输入到衣物处理装置的外部电力被中断，并且在向主要电力供应主要电力期间对辅助电源进行充电， 可以防止其他事故，并且由辅助电源控制通知装置，从而可以测量泄漏。

公开(公告)号：US07923732B2

公开(公告)日：2011-04-12

申请号：US12331361

申请日：2008-12-09

Applicant: Yu-Gwang Jeong ,  Young-Wook Lee ,  Sang-Gab Kim ,  Woo-Geun Lee ,  Min-Seok Oh ,  Jang-Soo Kim ,  Kap-Soo Yoon ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Seung-Hwan Shim ,  Sung-Hoon Yang ,  Ki-Hun Jeong

Inventor： Yu-Gwang Jeong ,  Young-Wook Lee ,  Sang-Gab Kim ,  Woo-Geun Lee ,  Min-Seok Oh ,  Jang-Soo Kim ,  Kap-Soo Yoon ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Seung-Hwan Shim ,  Sung-Hoon Yang ,  Ki-Hun Jeong

IPC: H01L29/00

CPC classification number: H01L27/127 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/66765

Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.

Abstract translation: 本发明的实施例涉及薄膜晶体管和显示面板的制造方法，包括在基板上形成包括栅电极的栅极线，在栅电极上形成栅绝缘层，在栅电极上形成本征半导体 栅极绝缘层，在本征半导体上形成非本征半导体，在外部半导体上形成包括源电极和漏电极的数据线，以及对源电极和漏极之间的非本征半导体的一部分进行等离子体处理，以形成 保护构件和保护构件的相应侧上的欧姆接触。 因此，可以省略用于蚀刻外部半导体和形成用于保护本征半导体的无机绝缘层的工艺，从而可以简化显示面板的制造工艺，可以降低制造成本，并且可以提高生产率。

公开(公告)号：US07834676B2

公开(公告)日：2010-11-16

申请号：US12357261

申请日：2009-01-21

Applicant: Woo-Geun Lee ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

Inventor： Woo-Geun Lee ,  Jean-Ho Song ,  Yeong-Keun Kwon ,  Min-Cheol Lee ,  Ki-Won Kim ,  Young-Wook Lee

IPC: G11C11/34

CPC classification number: G09G3/3648 ,  G09G2300/0413 ,  G09G2300/0819 ,  G09G2320/043

Abstract: A device for accounting for changes in characteristics of a transistor is presented. The device includes a transistor and a comparator receiving a feedback signal from the transistor and a reference signal. The comparator provides an output to a bias voltage generator. The bias voltage generator includes an input connected to the output of the comparator and an output connected to the transistor. In some embodiments of the invention the transistor is a double gate transistor and the bias voltage generator is applied to a top gate of the double gate transistor in order to control characteristics of the transistor such as turn on voltage.

Abstract translation: 提出了一种用于考虑晶体管特性变化的装置。 该器件包括晶体管和比较器，其接收来自晶体管的反馈信号和参考信号。 比较器向偏置电压发生器提供输出。 偏置电压发生器包括连接到比较器的输出的输入端和连接到晶体管的输出。 在本发明的一些实施例中，晶体管是双栅极晶体管，并且偏置电压发生器被施加到双栅晶体管的顶栅，以便控制晶体管的特性，例如导通电压。