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    Dynamically configurable pipeline
    61.
    发明授权
    Dynamically configurable pipeline 有权

    公开(公告)号：US10747700B1

    公开(公告)日：2020-08-18

    申请号：US15832546

    申请日：2017-12-05

    Applicant: Amazon Technologies, Inc.

    Inventor： Adiel Sarusi ,  Ron Diamant ,  Ori Weber ,  Erez Izenberg

    IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

    Abstract: Techniques disclosed herein relate to dynamically configurable multi-stage pipeline processing units. In one embodiment, a circuit includes a plurality of processing engines and a plurality of switches. Each of the plurality of processing engines includes an input port and an output port. Each of the plurality of switches comprises two input ports and two output ports. For each processing engine, the input port of the processing engine is electrically coupled to one of the switches, the output port of the processing engine is electrically coupled to another one of the switches, and the input port of the processing engine is electrically coupled to the output port of each of the processing engines by the switches.

    FLEXIBLE REMOTE DIRECT MEMORY ACCESS
    62.
    发明申请
    FLEXIBLE REMOTE DIRECT MEMORY ACCESS 审中-公开

    公开(公告)号：US20200151137A1

    公开(公告)日：2020-05-14

    申请号：US16702187

    申请日：2019-12-03

    Applicant: Amazon Technologies, Inc.

    Inventor： Erez Izenberg ,  Leah Shalev ,  Nafea Bshara ,  Guy Nakibly ,  Georgy Machulsky

    IPC: G06F15/167 ,  G06F16/22 ,  H04L29/06

    Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

    Packet processing cache
    63.
    发明授权
    Packet processing cache 有权

    公开(公告)号：US10298496B1

    公开(公告)日：2019-05-21

    申请号：US15716036

    申请日：2017-09-26

    Applicant: Amazon Technologies, Inc.

    Inventor： Guy Nakibly ,  Benzi Denkberg ,  Erez Izenberg ,  Nafea Bshara ,  Uri Leder ,  Ofer Frishman

    IPC: H04L12/747 ,  H04L12/861 ,  G06F12/0802 ,  H04L29/06 ,  H04L12/931

    Abstract: A data or packet processing device such as a network interface controller may include cache control logic that is configured to receive a first request for processing a first data packet associated with the queue identifier, and obtain a set of memory descriptors associated with the queue identifier from the memory. The set of descriptors can be stored in the cache. When a second request for processing a second data packet associated with the queue identifier is received, the cache control logic can determine that the cache is storing memory descriptors for processing the second data packet, and provide the memory descriptors used for processing the second packet.

    Configurable logic platform
    64.
    发明授权
    Configurable logic platform 有权

    公开(公告)号：US10223317B2

    公开(公告)日：2019-03-05

    申请号：US15279232

    申请日：2016-09-28

    Applicant: Amazon Technologies, Inc.

    Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

    IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

    Hardware security accelerator
    65.
    发明授权
    Hardware security accelerator 有权

    公开(公告)号：US10212138B1

    公开(公告)日：2019-02-19

    申请号：US14980664

    申请日：2015-12-28

    Applicant: AMAZON TECHNOLOGIES, INC.

    Inventor： Ron Diamant ,  Nafea Bshara ,  Leah Shalev ,  Erez Izenberg

    IPC: H04L29/08 ,  H04L29/06 ,  H04L9/14

    Abstract: A hardware security accelerator includes a configurable parser that is configured to receive a packet and to extract from the packet headers associated with a set of protocols. The security accelerator also includes a packet type detection unit to determine a type of the packet in response to the set of protocols and to generate a packet type identifier indicative of the type of the packet. A configurable security unit includes a configuration unit and a configurable security engine. The configuration unit configures the configurable security engine according to the type of the packet and to content of at least one of the headers extracted from the packet. The configurable security engine performs security processing of the packet to provide at least one security result.

    HYBRID REMOTE DIRECT MEMORY ACCESS
    67.
    发明申请
    HYBRID REMOTE DIRECT MEMORY ACCESS 审中-公开
    混合远程直接存储器访问

    公开(公告)号：US20170075857A1

    公开(公告)日：2017-03-16

    申请号：US15360853

    申请日：2016-11-23

    Applicant: Amazon Technologies, Inc.

    Inventor： Erez Izenberg ,  Leah Shalev ,  Georgy Machulsky ,  Nafea Bshara

    IPC: G06F15/173 ,  G06F3/06 ,  H04L29/08

    CPC classification number: G06F15/17331 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/067 ,  H04L67/1097

    Abstract: According to an embodiment of the invention there may be provided a method for hybrid remote direct memory access (RDMA), the method may include: (i) receiving, by a first computer, a packet that was sent over a network from a second computer; wherein the packet may include data and metadata; (ii) determining, in response to the metadata, whether the data should be (a) directly written to a first application memory of the first computer by a first hardware accelerator of the first computer; or (b) indirectly written to the first application memory; (iii) indirectly writing the data to the first application memory if it determined that the data should be indirectly written to the first application memory; (iv) if it determined that the data should be directly written to the first application memory then: (iv.a) directly writing, by the first hardware accelerator the data to the first application memory without writing the data to any buffer of the operating system; and (iv.b) informing a first RDMA software module, by the first hardware accelerator, that the data was directly written to the first application memory; and (v) notifying, by the first RDMA software module, a second computer about a completion of an RDMA transaction during which the data was directly written to the first application memory.

    Abstract translation: 根据本发明的实施例，可以提供一种用于混合远程直接存储器访问（RDMA）的方法，所述方法可以包括：（i）由第一计算机接收通过网络从第二计算机发送的分组 ; 其中所述分组可以包括数据和元数据; （ii）响应于所述元数据确定所述数据是否应当（a）由所述第一计算机的第一硬件加速器直接写入所述第一计算机的第一应用存储器; 或（b）间接写入第一个应用程序内存; （iii）如果确定数据应间接写入第一应用存储器，则将数据间接写入第一应用存储器; （iv）如果确定数据应直接写入第一应用存储器，则：（iv.a）由第一硬件加速器将数据直接写入第一应用存储器，而不将数据写入任何操作缓冲器 系统; 和（iv.b）通过第一硬件加速器通知第一RDMA软件模块将数据直接写入第一应用存储器; 以及（v）由第一RDMA软件模块通知第二台计算机，其中数据被直接写入到第一应用存储器中，完成RDMA事务。

    Clock synchronization in a network using a distributed pulse signal
    70.
    发明授权
    Clock synchronization in a network using a distributed pulse signal 有权

    公开(公告)号：US11967964B1

    公开(公告)日：2024-04-23

    申请号：US17709939

    申请日：2022-03-31

    Applicant: Amazon Technologies, Inc.

    Inventor： Noam Katz ,  Said Bshara ,  Erez Izenberg ,  Noam Attias

    IPC: H03L7/10 ,  G11C7/10 ,  H03L7/083 ,  H03L7/199

    CPC classification number: H03L7/103 ,  G11C7/1039 ,  H03L7/083 ,  H03L7/199

    Abstract: A clock disciplining scheme uses a pulse per second (PPS) signal that is distributed throughout a network to coordinate timing. In determining the time, jitter can occur due to latency between detection of the PPS signal and a software interrupt generated there from. This jitter affects the accuracy of the clock disciplining process. To eliminate the jitter, extra hardware is used to capture when the PPS signal occurred relative to a hardware clock counter associated with the clock disciplining software. In one embodiment, the extra hardware can be a sampling logic, which captures a state of a hardware clock counter upon PPS detection. In another embodiment, the extra hardware can initiate a counter that calculates a delay by the clock disciplining software in reading the hardware clock counter. The disciplining software can then subtract the calculated delay from a hardware clock counter to obtain the original PPS signal.

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