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    Embedded flat film molding
    61.
    发明授权
    Embedded flat film molding 有权

    公开(公告)号：US06900508B2

    公开(公告)日：2005-05-31

    申请号：US10123685

    申请日：2002-04-16

    Applicant: Anthony M. Chiu ,  Harry Michael Siegel

    Inventor： Anthony M. Chiu ,  Harry Michael Siegel

    IPC: G06K9/00 ,  H01L27/14

    CPC classification number: G06K9/0002

    Abstract: A flat filter layer is received between upper and lower mold portions of a mold for packaging an integrated circuit sensor device, held by the mold over and in contact with the integrated circuit's sensing surface, in light compression between the sensing surface and a mold surface. The filter layer includes slots allowing passage of injected encapsulating material to cover the integrated circuit die, with overlap portions embedded in the encapsulating material, while preventing such encapsulating material from flowing onto the sensing surface. The filter layer may be, for example, a liquid and/or light filter, and may include a protective or supportive backing. The filter is thus affixed to the packaged integrated circuit sensor device, while mold residue is reduced and mold life extended.

    Surface mount package for linear array sensors
    62.
    发明授权
    Surface mount package for linear array sensors 有权
    用于线性阵列传感器的表面贴装封装

    公开(公告)号：US06818963B1

    公开(公告)日：2004-11-16

    申请号：US09656985

    申请日：2000-09-07

    Applicant: Anthony M. Chiu

    Inventor： Anthony M. Chiu

    IPC: H01L310203

    CPC classification number: H01L25/042 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H05K1/181 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: In linear arrays of charge coupled device photosensors, sensor integrated circuits are contained in surface mountable packaging allowing individual segments to be soldered into place within the array. For solder-mountable packaging, unencapsulated sensor circuits are mounted onto a lead frame strip with the space between the circuits equaling the width of a singulation saw. After die mounting and wire bonding, a continuous strip of plastic or resin molding covers the wire bonds on one side and the edge of the silicon on the other, protecting the lead frame strip and other parts, leaving the active sensor area exposed. The lead frame is then trimmed and formed in a conventional manner, and the packaged sensor circuits are separated with a singulation saw cutting between the circuits. The resulting self-contained device may then be surface mounted within a linear array with solder rather than depending on Chip On Board technology. Leads are preferably soldered to the board on only one side, with the other side floating freely over the appropriate contacts for ease of mechanical adjustment. Individual sensor segments within the array may be readily removed and replaced in the event of a defect.

    Abstract translation: 在电荷耦合器件光电传感器的线性阵列中，传感器集成电路包含在可表面安装的封装中，允许将各个段焊接到阵列内的适当位置。 对于可焊接的封装，未封装的传感器电路安装在引线框架条上，电路之间的空间等于单锯的宽度。 在模具安装和引线接合之后，连续的塑料或树脂模制条覆盖一侧上的引线键合和硅的边缘，从而保护引线框架条和其他部件，从而使有源传感器区域暴露。 然后以常规方式修剪和形成引线框架，并且封装的传感器电路在电路之间用切割锯切割分开。 然后，所得到的独立装置可以用焊料表面安装在线性阵列内，而不依赖于板上芯片技术。 引线优选仅在一侧焊接到板上，另一侧在适当的触点上自由浮动以便于机械调节。 在发生缺陷的情况下，阵列内的各个传感器段可以容易地移除和更换。

    Low cost heat sink for packaged semiconductor device
    63.
    发明授权
    Low cost heat sink for packaged semiconductor device 失效
    用于封装半导体器件的低成本散热片

    公开(公告)号：US06326679B1

    公开(公告)日：2001-12-04

    申请号：US08533585

    申请日：1995-09-25

    Applicant: Anthony M. Chiu ,  Robert Alvarez

    Inventor： Anthony M. Chiu ,  Robert Alvarez

    IPC: H01L23495

    CPC classification number: H01L23/4334 ,  H01L23/49541 ,  H01L24/50 ,  H01L2924/14 ,  Y10T29/49121 ,  H01L2924/00

    Abstract: The invention disclosed herein is a device and method in which a heat sink (22) is attached to support leads (18) of a leadframe (10) via a welding or mechanical joining technique. The method is performed prior to semiconductor device packaging and is usually performed after the leadframe is etched or stamped, and before it is cut into strips.

    Abstract translation: 本文公开的本发明是一种其中通过焊接或机械连接技术将散热器（22）附接到引线框架（10）的引线（18）的装置和方法。 该方法在半导体器件封装之前执行，并且通常在引线框被蚀刻或冲压之后并且在其被切割成条之前进行。

    Low-profile socketed packaging system with land-grid array and thermally conductive slug
    64.
    发明授权
    Low-profile socketed packaging system with land-grid array and thermally conductive slug 失效
    薄型插座封装系统，具有阵列阵列和导热块

    公开(公告)号：US06113399A

    公开(公告)日：2000-09-05

    申请号：US099054

    申请日：1998-06-17

    Applicant: Michael J. Hundt ,  Anthony M. Chiu

    Inventor： Michael J. Hundt ,  Anthony M. Chiu

    IPC: H01R33/76 ,  H01L23/32 ,  H01L23/40 ,  H01R12/00 ,  H05K7/10 ,  H05K7/20 ,  H01R1/00

    CPC classification number: H05K7/1069 ,  H01L23/4093 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/181

    Abstract: A socketed integrated circuit packaging system, including a packaged integrated circuit and a socket therefor, is disclosed. The integrated circuit package includes a device circuit board to which a thermally conductive slug is mounted; the underside of the device circuit board has a plurality of lands arranged in an array. The integrated circuit chip is mounted to the slug, through a hole in the device circuit board, and is wire-bonded to the device circuit board and thus to the lands on the underside. The socket is a molded frame, having a hole therethrough to receive the conductive slug of the integrated circuit package; the socket may also have its own thermally conductive slug disposed within the hole of the frame. The socket has spring contact members at locations matching the location of the lands on the device circuit board. The integrated circuit package may be inserted into the socket frame, held there by a metal or molded clip. A low profile, low cost, and high thermal conductivity package and socket combination, is thus produced.

    Abstract translation: 公开了一种插座集成电路封装系统，包括封装集成电路及其插座。 集成电路封装包括安装导热块的器件电路板; 器件电路板的下侧具有排列成阵列的多个焊盘。 集成电路芯片通过器件电路板上的一个孔安装到芯块上，并且被引线接合到器件电路板，从而连接到底面的焊盘上。 插座是模制框架，具有穿过其中的孔以接收集成电路封装的导电块; 插座还可以具有设置在框架的孔内的其自身的导热块。 插座在与设备电路板上的焊盘的位置匹配的位置处具有弹簧接触构件。 集成电路封装可以插入插座框架中，通过金属或模制夹子保持在该框架中。 因此，制造了薄型，低成本和高导热性的封装和插座组合。

    Wafer burn-in and test system
    67.
    发明授权
    Wafer burn-in and test system 失效
    晶圆老化和测试系统

    公开(公告)号：US5444366A

    公开(公告)日：1995-08-22

    申请号：US191847

    申请日：1994-02-04

    Applicant: Anthony M. Chiu

    Inventor： Anthony M. Chiu

    IPC: G01R31/28 ,  G01R31/02

    CPC classification number: G01R31/2856 ,  G01R31/2863

    Abstract: An interconnection system and method of testing and performing burn-in of semiconductor devices prior to separation from the semiconductor wafer on which the devices are formed includes forming interconnection layers of contacts and conductors over the devices and then testing and performing burn-in on the devices. Faulty devices are disconnected from the conductors prior to performing additional test and burn-in. The interconnections are removed prior to separating the device on the wafer, and prior to further possible tests and packaging.

    Abstract translation: 在与形成器件的半导体晶片分离之前测试和执行半导体器件的老化的互连系统和方法包括在器件上形成触点和导体的互连层，然后在器件上测试和执行老化 。 在进行额外的测试和老化之前，有故障的设备与导体断开连接。 在将器件分离在晶片上之前，以及在进一步可能的测试和封装之前，互连被去除。

    Three dimensional multi-chip module with integral heat sink
    68.
    发明授权
    Three dimensional multi-chip module with integral heat sink 失效
    具有集成散热器的三维多芯片模块

    公开(公告)号：US5359493A

    公开(公告)日：1994-10-25

    申请号：US88996

    申请日：1993-07-09

    Applicant: Anthony M. Chiu

    Inventor： Anthony M. Chiu

    IPC: H01L23/40 ,  H01L25/10 ,  H05K7/20

    CPC classification number: H01L23/4006 ,  H01L25/18 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2924/0002

    Abstract: The invention is to a three dimensional circuit module constructed around a heat sink 10. A large integrated circuit component 21 such as a Micro Processing Unit for a computer is mounted over contact pads 27 on a printed wiring board 20. Also mounted to contact pads 27 on the printed wiring board are submodules 11, 12, 24, 25 that have wiring patterns interconnected to other circuit components 13-17, such as high power memory devices. The printed circuit submodules are mounted on the sides of the heat sink.

    Abstract translation: 本发明涉及一种围绕散热器10构建的三维电路模块。诸如用于计算机的微处理单元的大型集成电路部件21安装在印刷线路板20上的接触焊盘27上。还安装到接触垫27 在印刷电路板上的子模块11,12,24,25具有与其它电路部件13-17互连的布线图案，例如高功率存储器件。 印刷电路子模块安装在散热器的侧面。

    Folded bus bar leadframe and method of making
    69.
    发明授权
    Folded bus bar leadframe and method of making 失效
    折叠母线引线框架及其制作方法

    公开(公告)号：US5358598A

    公开(公告)日：1994-10-25

    申请号：US186840

    申请日：1994-01-26

    Applicant: Anthony M. Chiu

    Inventor： Anthony M. Chiu

    IPC: H01L23/50 ,  H01L23/495 ,  B44C1/22 ,  C23F1/00

    CPC classification number: H01L23/49551 ,  H01L23/4951 ,  H01L2224/73215 ,  Y10T29/49121

    Abstract: A leadframe has a bus bar extending between two lead fingers on the leadframe. The bus bar and lead fingers are etched to reduce the thickness thereof, and the bus bar is folded under the lead finger, but insulated therefrom by a strip of insulating material. An adhesive is applied to the bus bar to attached it and the leadframe to the surface of a semiconductor chip.

    Abstract translation: 引线框架具有在引线框架上的两个引线指之间延伸的汇流条。 母线和铅指被蚀刻以减小其厚度，并且母线在引线指下折叠，但是通过绝缘材料条绝缘。 将粘合剂施加到汇流条上，将其引线框架连接到半导体芯片的表面。

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