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    Error Detection Circuitry For Use With Memory
    63.
    发明申请
    Error Detection Circuitry For Use With Memory 有权
    与内存一起使用的错误检测电路

    公开(公告)号：US20160253227A1

    公开(公告)日：2016-09-01

    申请号：US14633062

    申请日：2015-02-26

    Applicant: ARM Limited

    Inventor： Andy Wangkun Chen ,  Mudit Bhargava ,  Paul Meyer ,  Vikas Chandra

    IPC: G06F11/07 ,  G06F11/08 ,  G06F11/10

    CPC classification number: G06F11/076 ,  G06F11/085 ,  G06F11/1012 ,  G06F11/1016

    Abstract: Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.

    Abstract translation: 本文描述的各种实现可以指代并且可以涉及用于与存储器一起使用的错误检测电路。 在一个实现中，集成电路可以包括具有多行存储器单元的存储器阵列，其中相应的行被配置为存储对应于数据字的数据字和一个或多个校验位。 集成电路还可以包括耦合到相应行并且被配置为基于检测存储在相应行中的数据字中的一个或多个位错误来生成一个或多个标志位值的在线错误检测电路。 集成电路还可以包括错误校正电路，其配置为响应于一个或多个生成的标志位值来校正存储在相应行中的数据字中的一个或多个位错误。

    Memory circuitry using write assist voltage boost
    64.
    发明授权
    Memory circuitry using write assist voltage boost 有权
    使用写辅助电压提升的存储电路

    公开(公告)号：US09142266B2

    公开(公告)日：2015-09-22

    申请号：US14083619

    申请日：2013-11-19

    Applicant: ARM LIMITED

    Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Gus Yeung ,  Bo Zheng ,  George Lattimore

    IPC: G11C7/00 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C7/22 ,  G11C5/14

    CPC classification number: G11C8/12 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

    Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

    Abstract translation: 在包括位单元6的阵列4的存储器2中，写入驱动器电路14使用在写入操作期间被提升到低于正常电平的升压写入信号。 列选择晶体管16由列选择电路12驱动。当列被选择时，列选择信号被提升到低于正常水平，并且当选择列时升高到高于正常水平。 在列选择电路12内采用电压升压电路，例如电荷泵20,22，以实现列选择信号的这些提升电平。

    Configurable scan chain architecture for multi-port memory
    65.
    发明授权
    Configurable scan chain architecture for multi-port memory 有权

    公开(公告)号：US12300338B2

    公开(公告)日：2025-05-13

    申请号：US17953271

    申请日：2022-09-26

    Applicant: Arm Limited

    Inventor： Andy Wangkun Chen ,  Vianney Antoine Choserot ,  Yew Keong Chong ,  Khushal Gelda

    IPC: G11C29/32 ,  G11C29/12 ,  G11C29/54

    Abstract: Various implementations described herein are related to a device having first datapath circuitry with input devices that receive data from a number of write ports and provide first data. The device may have second datapath circuitry with logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal. The device may have third datapath circuitry with output devices that receive the first data from the logic gates and provide second data to a number of read ports. Also, the number of read ports is greater than the number of write ports.

    POWER SAVING MODE CONTROL FOR A MEMORY INSTANCE
    66.
    发明申请
    POWER SAVING MODE CONTROL FOR A MEMORY INSTANCE 有权

    公开(公告)号：US20250103129A1

    公开(公告)日：2025-03-27

    申请号：US18474400

    申请日：2023-09-26

    Applicant: Arm Limited

    Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Munish Kumar ,  Vivek Asthana ,  Andrew John Turner ,  Alex James Waugh

    IPC: G06F1/3296 ,  G06F12/0815

    Abstract: A memory instance comprises a plurality of banks of storage cells to store data values, and input/output circuitry shared between the plurality of banks for receiving write data or outputting read data. Each bank of storage cells supports a power saving mode and an operational mode. A control interface receives power control signals for controlling use of the power saving mode. Bank power control circuitry individually controls, for each of a plurality of subsets of banks of storage cells within the same memory instance, whether that subset of banks is in the power saving mode based on the power control signals. For at least one setting for the power control signals, one subset of banks is in the power saving mode while another subset of banks in the same memory instance is in the operational mode. Also disclosed is power control circuitry which selects the power mode to use for each subset of banks and generates the power control signals.

    Multi-Transistor Bitcell Structure
    67.
    发明申请
    Multi-Transistor Bitcell Structure 有权

    公开(公告)号：US20250078912A1

    公开(公告)日：2025-03-06

    申请号：US18240875

    申请日：2023-08-31

    Applicant: Arm Limited

    Inventor： Andy Wangkun Chen ,  Rahul Mathur

    IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

    Abstract: Various implementations described herein are directed to a device having first transistors arranged as cross-coupled inverters coupled between a disconnect node and ground. The device may have second transistors arranged as passgates coupled between the cross-coupled inverters and bitlines. The device may have third transistors coupled between a voltage supply and the disconnect node.

    Memory Testing Techniques
    70.
    发明公开
    Memory Testing Techniques 审中-公开

    公开(公告)号：US20240136006A1

    公开(公告)日：2024-04-25

    申请号：US18400738

    申请日：2023-12-29

    Applicant: Arm Limited

    Inventor： Andy Wangkun Chen ,  Yannis Jallamion-Grive ,  Cyrille Nicolas Dray

    IPC: G11C29/42 ,  G06F11/10 ,  G06F11/27 ,  G11C29/00 ,  G11C29/02 ,  G11C29/34

    CPC classification number: G11C29/42 ,  G06F11/102 ,  G06F11/106 ,  G06F11/27 ,  G11C29/025 ,  G11C29/34 ,  G11C29/781 ,  G11C29/802 ,  G11C2029/1802

    Abstract: Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.

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