Abstract:
Disclosed is a method of fluorescent detection of a nucleic acid. The method comprises contacting to the nucleic acid a bis-dicationic aryl furan compound, such as 2,5-bis[4-(4,5,6,7-tetrahydro-1H-1,3-diazepin-2-yl) phenyl] furan; 2,5-bis{[4-(N-isopropyl) amidino] phenyl}furan; and physiologically acceptable salts thereof, and exposing the nucleic acid to light at a frequency to induce fluorescence of the compound. A method for fluorescent detection of cytoskeleton elements, and novel bis-dicationic aryl furan compounds are also disclosed.
Abstract:
A method and system to reduce card transaction fee while enabling the payment from dynamically mapped retail cards. Being a mapping and API based solution, technical integration with any bank is much easier with very less cost while enabling the easy future enhancements. With this Solution customer will map all his retail card to any one credit card on app and while making the payments solutions will enable bank to take payment from the respective retail card for retailer. With this mapping-based solution customer will get same functionality, if due to any reason he is not able to use his mobile for payment and use the credit card mapped.
Abstract:
Technologies for input compute offloading of digital content include a source computing device for wirelessly transmitting the digital content to a destination computing device. The destination computing device is configured to detect inputs initiated by a user on a display of the destination computing device and transmit input characteristics to the source computing device that are usable by the source computing device to render the digital content to include one or more objects based on the one or more input characteristics. The source computing device is configured to receive the input characteristics from the destination computing device and render the digital content to include one or more objects based on the one or more input characteristics. Other embodiments are described and claimed.
Abstract:
Embodiments of the present disclosure provide techniques and configurations for an apparatus for opportunistic measurements of user's physiological context. In one instance, the apparatus may comprise a work surface that includes one or more electrodes disposed on the work surface to directly or indirectly contact with user's portions of limbs, when the user's portions of limbs are disposed on the work surface to interact with the apparatus, to obtain one or more parameters of user's physiological context; and circuitry coupled with the electrodes to detect direct or indirect contact between the user's portions of limbs and the electrodes and on detection, collect the parameters of the user's physiological context while the direct or indirect contact is maintained. Other embodiments may be described and/or claimed.
Abstract:
Systems and methods may provide for detecting an event on a computing device having an embedded keyboard with a default mapping of keys to functions and disabling a first subset of keys on the embedded keyboard in response to the event. Additionally, a second subset of keys on the embedded keyboard may be re-mapped to one or more different functions if an application running on the computing device supports keyboard re-mapping. In one example, re-mapping the second subset of keys includes grouping two or more keys in the second subset into a common function.
Abstract:
Methods and apparatus relating to processor extensions for execution of secure embedded containers are described. In an embodiment, a scalable solution for manageability function is provided, e.g., for UMPC environments or otherwise where utilizing a dedicated processor or microcontroller for manageability is inappropriate or impractical. For example, in an embodiment, an OS (Operating System) or VMM (Virtual Machine Manager) Independent (generally referred to herein as “OI”) architecture involves creating one or more containers on a processor by dynamically partitioning resources (such as processor cycles, memory, devices) between the HOST OS/VMM and the OI container. Other embodiments are also described and claimed.
Abstract translation:描述与用于执行安全嵌入式容器的处理器扩展有关的方法和装置。 在一个实施例中,提供了用于可管理性功能的可扩展解决方案,例如对于UMPC环境,或者其他利用专用处理器或微控制器进行可管理性是不合适或不切实际的。 例如,在一个实施例中,OS(操作系统)或VMM(虚拟机管理器)独立(本文通常称为“OI”)架构涉及通过动态地划分资源(例如处理器周期)来在处理器上创建一个或多个容器 ,内存,设备)在HOST OS / VMM和OI容器之间。 还描述和要求保护其他实施例。
Abstract:
In an embodiment, a first portion of a cache memory is associated with a first core. This first cache memory portion is of a distributed cache memory, and may be dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores (including the first core) according to an addressing mode, which itself is dynamically controllable. Other embodiments are described and claimed.
Abstract:
A method to adjust operation of a network controller of a device is disclosed. The method may include receiving contextual data from a sensor communicatively coupled to the device. The method may also include analyzing the contextual data to determine the context of the device. The method may also include modifying the network controller operation based on the analyzed contextual data.
Abstract:
In an embodiment, a processor includes a graphics domain including a graphics engines each having at least one execution unit. The graphics domain is to schedule a touch application offloaded from a core domain to at least one of the plurality of graphics engines. The touch application is to execute responsive to an update to a doorbell location in a system memory coupled to the processor, where the doorbell location is written responsive to a user input to the touch input device. Other embodiments are described and claimed.
Abstract:
An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.