公开(公告)号：US20130002357A1

公开(公告)日：2013-01-03

申请号：US13173791

申请日：2011-06-30

申请人： Axel Thomsen ,  Zhongda Wang ,  Sai Chu Wong ,  Yunteng Huang

发明人： Axel Thomsen ,  Zhongda Wang ,  Sai Chu Wong ,  Yunteng Huang

IPC分类号： H03G3/34

CPC分类号： H03G3/34 ,  H03G3/3042

摘要： A power control circuit is coupled to receive a feedback signal from a power amplifier (PA) and generate a control signal to control a variable gain amplifier (VGA) coupled to an input to the PA based on the feedback signal. The power control circuit may include, in one embodiment, a mute circuit to generate a mute signal to be provided to the VGA when the control signal is less than a first level and a clamp circuit to clamp a control voltage used to generate the control signal from exceeding a threshold level.

摘要翻译： 功率控制电路被耦合以从功率放大器（PA）接收反馈信号，并产生控制信号，以根据反馈信号控制耦合到PA的输入的可变增益放大器（VGA）。 在一个实施例中，功率控制电路可以包括静音电路，以在控制信号小于第一电平时产生要提供给VGA的静音信号，以及钳位电路来钳位用于产生控制信号的控制电压 超过阈值水平。

公开(公告)号：US07825708B2

公开(公告)日：2010-11-02

申请号：US12249457

申请日：2008-10-10

申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

IPC分类号： H03L7/06

CPC分类号： H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

摘要： A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.

摘要翻译： 第一锁相环（PLL）电路包括用于从振荡器接收定时参考信号的输入端，提供振荡器输出信号的可控振荡器电路和多模反馈分频器电路。 第二控制回路电路通过选择电路可选地耦合，以将数字控制值（M）提供给第一回路电路的多模反馈分配器电路，从而控制振荡器输出信号。 当第二控制回路被耦合以将控制值提供给反馈分配器电路时，根据在分频器电路处的振荡器输出信号和耦合到第二控制回路电路的参考信号之间的检测到差异来确定控制值。 当第二控制环路电路不耦合以控制第一PLL电路时，第一PLL电路接收数字控制值以控制反馈分频器的分频比，数字控制值至少部分地根据存储的控制 存储在非易失性存储器中的值，所存储的控制值对应于振荡器输出信号的期望频率。

公开(公告)号：US20100117703A1

公开(公告)日：2010-05-13

申请号：US12269984

申请日：2008-11-13

申请人： Zhipeng Zhu ,  Axel Thomsen

发明人： Zhipeng Zhu ,  Axel Thomsen

IPC分类号： H03K3/00 ,  G05F1/10

CPC分类号： H03K5/082 ,  H03K19/00361

摘要： Techniques reduce the effects of power supply noise on a signal provided by a single-ended complementary metal-oxide semiconductor (i.e., CMOS) input buffer circuit capable of receiving an input signal having one of a variety of acceptable formats, while generating the signal to have substantially the same duty cycle as the input signal. The techniques include one or more of AC coupling, hysteresis, and voltage biasing applied to the input buffer circuit.

摘要翻译： 技术降低电源噪声对单端互补金属氧化物半导体（即CMOS）输入缓冲电路提供的信号的影响，该电路能够接收具有多种可接受格式之一的输入信号，同时产生信号 具有与输入信号基本相同的占空比。 这些技术包括施加到输入缓冲器电路的AC耦合，迟滞和电压偏置中的一个或多个。

公开(公告)号：US07498656B2

公开(公告)日：2009-03-03

申请号：US10813886

申请日：2004-03-31

申请人： Ligang Zhang ,  David Pietruszynski ,  Axel Thomsen ,  Kevin G. Smith

发明人： Ligang Zhang ,  David Pietruszynski ,  Axel Thomsen ,  Kevin G. Smith

IPC分类号： H01F27/28

CPC分类号： H01L23/552 ,  H01F2017/008 ,  H01L23/645 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2224/0401

摘要： An improved electromagnetic shielding structure has been discovered. In one embodiment of the invention, an apparatus includes an inductor and an electrically conductive enclosure that electromagnetically shields the inductor. The electrically conductive enclosure has an aperture at least as large as the inductor. The aperture is substantially centered around a projected surface of the inductor. The apparatus may include one or more electrically conductive links extending across the aperture and electrically coupled to the electrically conductive enclosure. The electrically conductive links reduce an effect of electromagnetic signals external to the electrically conductive enclosure on the inductor.

摘要翻译： 已经发现了改进的电磁屏蔽结构。 在本发明的一个实施例中，一种装置包括电感器和电磁屏蔽电感器的导电外壳。 导电外壳具有至少与电感器一样大的孔径。 孔径基本上以电感器的投影表面为中心。 该装置可以包括一个或多个延伸穿过孔并且电耦合到导电外壳的导电链路。 导电链路降低电感器上导电外壳外部的电磁信号的影响。

公开(公告)号：US07352207B2

公开(公告)日：2008-04-01

申请号：US11239944

申请日：2005-09-30

申请人： Akhil K. Garlapati ,  Axel Thomsen

发明人： Akhil K. Garlapati ,  Axel Thomsen

IPC分类号： H03K19/094 ,  H03K19/0175 ,  H01L5/00

CPC分类号： H03F3/45188 ,  H03F3/3061 ,  H03F3/45654 ,  H03F3/45708

摘要： A complementary metal-oxide semiconductor output driver provides a differential output signal having a particular differential voltage swing and a particular common mode voltage to a differential output node for various types of load circuits coupled to the differential output node. The load circuit may have any impedance within a particular impedance range. A current source provides a current with a variable current component that adjusts the differential voltage swing of the differential output signal. A common mode feedback circuit adjusts the common mode voltage of the differential output signal by sourcing current to the differential output node or sinking current from the differential output node. At least a portion of a current flowing into a load circuit coupled to the differential node is provided by the current source, thereby reusing current from the current source.

摘要翻译： 互补金属氧化物半导体输出驱动器为耦合到差分输出节点的各种类型的负载电路提供具有特定差分电压摆幅和特定共模电压的差分输出信号到差分输出节点。 负载电路可以在特定阻抗范围内具有任何阻抗。 电流源为电流提供调节差分输出信号的差分电压摆幅的可变电流分量。 共模反馈电路通过向差分输出节点提供电流或从差分输出节点吸收电流来调整差分输出信号的共模电压。 流过耦合到差分节点的负载电路的电流的至少一部分由电流源提供，从而重新使用来自电流源的电流。

公开(公告)号：US07162506B1

公开(公告)日：2007-01-09

申请号：US11057450

申请日：2005-02-14

申请人： Axel Thomsen ,  Jerome E Johnston ,  Edwin Angel ,  Aryesh Amar

发明人： Axel Thomsen ,  Jerome E Johnston ,  Edwin Angel ,  Aryesh Amar

IPC分类号： G06F17/10

CPC分类号： H03H17/0294 ,  H03M3/392 ,  H03M3/462

摘要： In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

摘要翻译： 在具有模拟数字转换器的信号处理集成电路和具有时间分离的多个抽头的数字滤波器的情况下，当在复位或输入通道改变之后开始转换时，滤波器将具有不完整的输入数据集 输出计算的延迟输入从复位操作全部为零。 在复位之后，在数据填满过滤器管线的时间期间，输出值的计算将给出保存有关输入信息的结果，但不显示具有与完全设置的过滤器相同的缩放和频率内容的数据 。 集成电路有选择地提供两种模式，其中仅提供来自滤波器的完全确定的数据，或者提供来自滤波器的所有数据的另一种模式，包括不稳定的数据。 关于滤波器系数的知识可以由用户或用户进程利用来从未解决的数据中提取关于输入的信息。

公开(公告)号：US07141883B2

公开(公告)日：2006-11-28

申请号：US10463961

申请日：2003-06-18

申请人： Derrick C. Wei ,  Ying Shi ,  Kevin G. Smith ,  Steven P. Proffitt ,  Axel Thomsen ,  David M. Pietruszynski ,  Ligang Zhang

发明人： Derrick C. Wei ,  Ying Shi ,  Kevin G. Smith ,  Steven P. Proffitt ,  Axel Thomsen ,  David M. Pietruszynski ,  Ligang Zhang

IPC分类号： H01L23/48 ,  H01L23/552

CPC分类号： H01L23/552 ,  H01F2017/008 ,  H01L23/645 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2224/0401

摘要： An electromagnetically-shielded high-Q inductor may be fabricated within a multi-layer package substrate (MLS). The inductor is preferably constructed as a loop structure on a layer of the MLS, and a shielding structure is formed around the inductor to substantially enclose the inductor in a Faraday cage-like enclosure. The shielding structure includes a top plate formed above the inductor on another layer of the MLS, and a bottom plate formed on yet another layer of the MLS or on a layer of an integrated circuit die which is below and attached to the MLS, preferably using solder bumps. Shielding structure sidewalls may be formed by a ring of stacked vias or via channels. The inductor is preferably connected to stacked vias which provide a connection to the underlying integrated circuit die by way of additional solder bumps and cut-outs through the bottom plate of the shielding structure.

摘要翻译： 可以在多层封装衬底（MLS）内制造电磁屏蔽的高Q电感器。 电感器优选地构造为MLS层上的环路结构，并且围绕电感器形成屏蔽结构，以将电感器基本上包围在法拉第笼状壳体中。 屏蔽结构包括在MLS的另一层上形成在电感器上方的顶板，以及形成在MLS的另一层上的底板或集成电路管芯的下面并连接到MLS上的层，优选地使用 焊锡凸块 屏蔽结构侧壁可以由堆叠的通孔环或通孔形成。 电感器优选地连接到堆叠的通孔，其通过附加的焊料凸块和穿过屏蔽结构的底板的切口提供到下面的集成电路管芯的连接。

公开(公告)号：US20060119437A1

公开(公告)日：2006-06-08

申请号：US11270957

申请日：2005-11-10

申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell Hein ,  Derrick Wei

发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell Hein ,  Derrick Wei

IPC分类号： H03L7/00

CPC分类号： H03L7/0898 ,  H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/197 ,  H03L7/1976 ,  H03L7/23 ,  H03L7/235 ,  H03L2207/50 ,  H04J3/0688

摘要： A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.

摘要翻译： 电压控制时钟合成器包括接收定时参考信号的锁相环（PLL）电路，提供振荡器输出信号的可控振荡器电路，例如VCO，以及耦合到振荡器输出信号的反馈分频器电路。 振荡器输出信号的频率部分地根据用于产生确定反馈分频器电路的分频比的第一数字控制信号的存储值来确定。 存在于电压控制输入端的控制电压根据由存储的值确定的频率调整振荡器输出信号的频率。 控制电压被转换为第二数字信号，并用于与所存储的值组合确定第一数字控制信号。

公开(公告)号：US07047148B1

公开(公告)日：2006-05-16

申请号：US09695703

申请日：2000-10-25

申请人： Axel Thomsen

发明人： Axel Thomsen

IPC分类号： H03F1/26 ,  G01R31/00

CPC分类号： G01R29/26 ,  G01R31/316

摘要： The time required to measure 1/f noise for a device, such as an integrated circuit, can be shortened by applying offset to a chopper stabilized circuit and then using offset removal as a surrogate measure for 1/f noise performance.

摘要翻译： 通过对斩波稳定电路施加偏移，然后使用偏移消除作为1 / f噪声性能的替代测量，可以缩短测量设备（例如集成电路）1 / f噪声所需的时间。

公开(公告)号：US20060033546A1

公开(公告)日：2006-02-16

申请号：US11239943

申请日：2005-09-30

申请人： Yunteng Huang ,  Ligang Zhang ,  Axel Thomsen

发明人： Yunteng Huang ,  Ligang Zhang ,  Axel Thomsen

IPC分类号： G06F1/04

CPC分类号： G06F7/68 ,  H03L7/183 ,  H03L7/23

摘要： A PLL function may be implemented as a dual-loop structure having a first PLL circuit which generates an intermediate signal from the reference signal, and a second PLL circuit which generates an output signal from the intermediate signal. The intermediate signal frequency is preferably chosen at a value in which potential interference signals do not have much energy. The first loop preferably has low bandwidth to provide good input jitter attenuation, while second loop preferably has higher bandwidth to reduce phase noise of the output signal. The circuit preferably provides for a choice of several different intermediate frequencies to allow use where different intermediate frequencies may exist in each system. Moreover, in a system having two such dual-loop PLL circuits, each can be configured with a different intermediate frequency, so that interference from one to the other is reduced.

摘要翻译： PLL功能可以实现为具有从参考信号产生中间信号的第一PLL电路的双回路结构，以及从中间信号产生输出信号的第二PLL电路。 中间信号频率优选地被选择为其中潜在的干扰信号没有太多能量的值。 第一环路优选具有低带宽以提供良好的输入抖动衰减，而第二环路优选地具有较高带宽以减少输出信号的相位噪声。 该电路优选地提供几种不同中频的选择，以允许在每个系统中可能存在不同中频的应用。 此外，在具有两个这样的双回路PLL电路的系统中，每个都可以配置有不同的中频，从而减少了从一个到另一个的干扰。