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    High-speed divider with pulse-width control
    1.
    发明授权
    High-speed divider with pulse-width control 有权
    高速分频器具有脉冲宽度控制

    公开(公告)号：US07405601B2

    公开(公告)日：2008-07-29

    申请号：US11680026

    申请日：2007-02-28

    申请人： Akhil K. Garlapati ,  Lizhong Sun ,  Douglas F. Pastorello ,  Richard J. Juhn ,  Axel Thomsen

    发明人： Akhil K. Garlapati ,  Lizhong Sun ,  Douglas F. Pastorello ,  Richard J. Juhn ,  Axel Thomsen

    IPC分类号： H03K21/00

    CPC分类号： H03K23/66 ,  H03K21/10 ,  H03L7/0805 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093 ,  H03L7/193 ,  H03L7/1974 ,  H03L7/1976

    摘要： In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.

    摘要翻译： 在本发明的至少一个实施例中，一种用于将具有第一频率的第一信号除以分频比以产生较低频率信号的方法包括产生具有共同频率，第一脉冲宽度和不同相位的第一多个信号 。 第一组多个信号至少部分地基于具有第二脉冲宽度的至少一个信号。 至少部分地基于分频比，从多个脉冲宽度中选择第一脉冲宽度。 该方法包括顺序选择第一多个信号中的各个脉冲作为选择电路的输出信号，以产生具有低于第一频率的频率的输出信号。

    Output driver with common mode feedback
    2.
    发明授权
    Output driver with common mode feedback 有权
    具有共模反馈的输出驱动器

    公开(公告)号：US07352207B2

    公开(公告)日：2008-04-01

    申请号：US11239944

    申请日：2005-09-30

    申请人： Akhil K. Garlapati ,  Axel Thomsen

    发明人： Akhil K. Garlapati ,  Axel Thomsen

    IPC分类号： H03K19/094 ,  H03K19/0175 ,  H01L5/00

    CPC分类号： H03F3/45188 ,  H03F3/3061 ,  H03F3/45654 ,  H03F3/45708

    摘要： A complementary metal-oxide semiconductor output driver provides a differential output signal having a particular differential voltage swing and a particular common mode voltage to a differential output node for various types of load circuits coupled to the differential output node. The load circuit may have any impedance within a particular impedance range. A current source provides a current with a variable current component that adjusts the differential voltage swing of the differential output signal. A common mode feedback circuit adjusts the common mode voltage of the differential output signal by sourcing current to the differential output node or sinking current from the differential output node. At least a portion of a current flowing into a load circuit coupled to the differential node is provided by the current source, thereby reusing current from the current source.

    摘要翻译： 互补金属氧化物半导体输出驱动器为耦合到差分输出节点的各种类型的负载电路提供具有特定差分电压摆幅和特定共模电压的差分输出信号到差分输出节点。 负载电路可以在特定阻抗范围内具有任何阻抗。 电流源为电流提供调节差分输出信号的差分电压摆幅的可变电流分量。 共模反馈电路通过向差分输出节点提供电流或从差分输出节点吸收电流来调整差分输出信号的共模电压。 流过耦合到差分节点的负载电路的电流的至少一部分由电流源提供，从而重新使用来自电流源的电流。

    DUAL LOOP ARCHITECTURE USEFUL FOR A PROGRAMMABLE CLOCK SOURCE AND CLOCK MULTIPLIER APPLICATIONS
    5.
    发明申请
    DUAL LOOP ARCHITECTURE USEFUL FOR A PROGRAMMABLE CLOCK SOURCE AND CLOCK MULTIPLIER APPLICATIONS 有权
    双循环架构可用于可编程时钟源和时钟多路复用器应用

    公开(公告)号：US20090039968A1

    公开(公告)日：2009-02-12

    申请号：US12249457

    申请日：2008-10-10

    申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

    发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

    IPC分类号： H03L7/07

    CPC分类号： H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

    摘要： A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.

    摘要翻译： 第一锁相环（PLL）电路包括用于从振荡器接收定时参考信号的输入端，提供振荡器输出信号的可控振荡器电路和多模反馈分频器电路。 第二控制回路电路通过选择电路可选地耦合，以将数字控制值（M）提供给第一回路电路的多模反馈分配器电路，从而控制振荡器输出信号。 当第二控制回路被耦合以将控制值提供给反馈分配器电路时，根据在分频器电路处的振荡器输出信号和耦合到第二控制回路电路的参考信号之间的检测到差异来确定控制值。 当第二控制环路电路不耦合以控制第一PLL电路时，第一PLL电路接收数字控制值以控制反馈分频器的分频比，数字控制值至少部分地根据存储的控制 存储在非易失性存储器中的值，所存储的控制值对应于振荡器输出信号的期望频率。

    Dual loop architecture useful for a programmable clock source and clock multiplier applications
    6.
    发明授权
    Dual loop architecture useful for a programmable clock source and clock multiplier applications 有权
    双循环架构可用于可编程时钟源和时钟乘法器应用

    公开(公告)号：US07436227B2

    公开(公告)日：2008-10-14

    申请号：US10878218

    申请日：2004-06-28

    申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

    发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein

    IPC分类号： H03L7/06

    CPC分类号： H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

    摘要： A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.

    摘要翻译： 第一锁相环（PLL）电路包括用于从振荡器接收定时参考信号的输入端，提供振荡器输出信号的可控振荡器电路和多模反馈分频器电路。 第二控制回路电路通过选择电路可选地耦合，以将数字控制值（M）提供给第一回路电路的多模反馈分配器电路，从而控制振荡器输出信号。 当第二控制回路被耦合以将控制值提供给反馈分配器电路时，根据在分频器电路处的振荡器输出信号和耦合到第二控制回路电路的参考信号之间的检测到差异来确定控制值。 当第二控制环路电路不耦合以控制第一PLL电路时，第一PLL电路接收数字控制值以控制反馈分频器的分频比，数字控制值至少部分地根据存储的控制 存储在非易失性存储器中的值，所存储的控制值对应于振荡器输出信号的期望频率。

    Linear phase detector and charge pump
    7.
    发明授权
    Linear phase detector and charge pump 有权
    线性相位检测器和电荷泵

    公开(公告)号：US07400204B2

    公开(公告)日：2008-07-15

    申请号：US11168012

    申请日：2005-06-28

    申请人： Axel Thomsen ,  Ronald G. Spencer

    发明人： Axel Thomsen ,  Ronald G. Spencer

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0895 ,  H03D13/004 ,  H03L7/1976

    摘要： A phase detector detects a phase difference between a first and second signal received by a phase detector. A charge is supplied by a charge pump circuit that corresponds to the phase difference using a phase difference to charge conversion that is substantially linear and nonzero in a phase error region that includes a phase error transition region around a phase error of zero having both negative and positive phase error values. Dual determinations, q1 and q2, offset from each other are made of an appropriate charge for a given phase error between the first and second signals. The charge pump supplies as the total charge pump output a charge value representing a combination of q1 and q2, thereby providing a phase error to charge conversion that is substantially linear in the phase error transition region around zero. A first and second output of the phase detector circuit respectively supplying UP and DOWN signals to the charge pump circuit are delayed and supplied as additional outputs of the phase detector circuit and used in generating the dual charge determinations q1 and q2.

    摘要翻译： 相位检测器检测由相位检测器接收的第一和第二信号之间的相位差。 由相位差对应的电荷泵电路提供电荷，所述电荷泵电路使用在相位误差区域中基本为线性且非零的相位差的电荷转换，所述相位误差区域包括零​​相位误差为零的相位误差跃迁区域， 正相误差值。 对于第一和第二信号之间给定的相位误差，双重确定q1和q2彼此偏移由适当的电荷构成。 电荷泵作为总电荷泵输出表示q1和q2的组合的电荷值，从而在零相位误差过渡区域内提供基本为线性的电荷转换的相位误差。 分别向电荷泵电路提供UP和DOWN信号的相位检测器电路的第一和第二输出被延迟并作为相位检测器电路的附加输出提供，并用于产生双电荷确定q1和q2。

    Output driver with common mode feedback
    8.
    发明申请
    Output driver with common mode feedback 有权
    具有共模反馈的输出驱动器

    公开(公告)号：US20070075776A1

    公开(公告)日：2007-04-05

    申请号：US11239944

    申请日：2005-09-30

    申请人： Akhil Garlapati ,  Axel Thomsen

    发明人： Akhil Garlapati ,  Axel Thomsen

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45188 ,  H03F3/3061 ,  H03F3/45654 ,  H03F3/45708

    摘要： A complementary metal-oxide semiconductor output driver provides a differential output signal having a particular differential voltage swing and a particular common mode voltage to a differential output node for various types of load circuits coupled to the differential output node. The load circuit may have any impedance within a particular impedance range. A current source provides a current with a variable current component that adjusts the differential voltage swing of the differential output signal. A common mode feedback circuit adjusts the common mode voltage of the differential output signal by sourcing current to the differential output node or sinking current from the differential output node. At least a portion of a current flowing into a load circuit coupled to the differential node is provided by the current source, thereby reusing current from the current source.

    摘要翻译： 互补金属氧化物半导体输出驱动器为耦合到差分输出节点的各种类型的负载电路提供具有特定差分电压摆幅和特定共模电压的差分输出信号到差分输出节点。 负载电路可以在特定阻抗范围内具有任何阻抗。 电流源为电流提供调节差分输出信号的差分电压摆幅的可变电流分量。 共模反馈电路通过向差分输出节点提供电流或从差分输出节点吸收电流来调整差分输出信号的共模电压。 流过耦合到差分节点的负载电路的电流的至少一部分由电流源提供，从而重新使用来自电流源的电流。

    Multi-frequency clock synthesizer
    9.
    发明申请
    Multi-frequency clock synthesizer 有权
    多频时钟合成器

    公开(公告)号：US20060119402A1

    公开(公告)日：2006-06-08

    申请号：US11270954

    申请日：2005-11-10

    申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell Hein ,  Michael Petrowski

    发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell Hein ,  Michael Petrowski

    IPC分类号： H03B21/00

    CPC分类号： H03L7/23 ,  H03L7/0898 ,  H03L7/197 ,  H03L7/1976

    摘要： A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.

    摘要翻译： 锁相环（PLL）电路包括用于接收定时参考信号的输入端，耦合以接收定时参考信号的相位检测器电路，根据相位检测器电路的输出控制的可控振荡器电路，以及反馈分配器 电路具有耦合到相位检测器的输出端和耦合到可控振荡器电路的输入端。 锁相环电路根据频率选择机构耦合到输出具有任意频率关系的多个输出信号中的一个，所述频率选择机构包括一个或多个输入端，用于控制所述频率选择机构的分频比 反馈分频电路。 频率选择机构选择多个存储值中的一个。 选择的存储值至少部分地控制反馈分频器电路的分频比，从而提供能够在彼此具有任意关系的输出频率之间进行选择的引脚可编程器件。

    Phase selectable divider circuit
    10.
    发明申请
    Phase selectable divider circuit 有权
    相位可选分频电路

    公开(公告)号：US20050242848A1

    公开(公告)日：2005-11-03

    申请号：US10878198

    申请日：2004-06-28

    申请人： Lizhong Sun ,  Douglas Pastorello ,  Richard Juhn ,  Axel Thomsen

    发明人： Lizhong Sun ,  Douglas Pastorello ,  Richard Juhn ,  Axel Thomsen

    IPC分类号： H03K23/66 ,  H03L7/00 ,  H03L7/193 ,  H03L7/197

    CPC分类号： H03K23/66 ,  H03L7/193 ,  H03L7/1976

    摘要： A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is summed with a second value corresponding to a phase offset from the first phase to generate a sum indicative thereof. That sum is used to select a second one of the signals having a second phase as the next selector circuit output signal. As successive sums are generated, a pulse train is supplied by selector circuit having a desired frequency.

    摘要翻译： 相位选择分频电路包括接收具有共同频率和不同相位的多个信号的选择电路。 选择具有第一相位的多个信号中的一个作为选择器电路输出信号。 对应于第一相位的第一值与对应于从第一相位的相位偏移的第二值相加，以产生指示其的和。 该和用于选择具有第二相位的第二信号作为下一个选择器电路输出信号。 当产生连续的和时，由选择器电路提供具有期望频率的脉冲串。