公开(公告)号：US20120171827A1

公开(公告)日：2012-07-05

申请号：US13417900

申请日：2012-03-12

申请人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

发明人： Chengwen Pei ,  Kangguo Cheng ,  Herbert L. Ho ,  Subramanian S. Iyer ,  Byeong Y. Kim ,  Geng Wang ,  Huilong Zhu

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/945

摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.

摘要翻译： 提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和 内电极 以及位于沟槽电容器上方的半导体器件。 半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。 存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

公开(公告)号：US20120153431A1

公开(公告)日：2012-06-21

申请号：US13406664

申请日：2012-02-28

申请人： Brent A. Anderson ,  Andres Bryant ,  Herbert L. Ho ,  Edward J. Nowak

发明人： Brent A. Anderson ,  Andres Bryant ,  Herbert L. Ho ,  Edward J. Nowak

IPC分类号： H01L29/06

CPC分类号： H01L21/76224 ,  H01L27/10829 ,  H01L27/10867 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66181

摘要： Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).

摘要翻译： 公开了具有至少一个深沟槽隔离结构和深沟槽电容器的集成电路。 形成集成电路的方法包括单个蚀刻工艺，以分别同时形成用于深沟槽隔离结构的第一沟槽和第二沟槽以及深沟槽电容器。 在形成与第二沟槽的下部相邻的埋置的电容器板之后，沟槽衬有保形绝缘体层并填充有导电材料。 因此，对于深沟槽电容器，除了埋置的电容器板之外，保形绝缘体层用作电容器电介质和作为电容器板的导电材料。 在衬底中形成的浅沟槽隔离（STI）结构跨越第一沟槽的顶部封装在其中的导电材料，从而形成深沟槽隔离结构。

公开(公告)号：US08168507B2

公开(公告)日：2012-05-01

申请号：US12545116

申请日：2009-08-21

申请人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

发明人： Herbert L. Ho ,  Naoyoshi Kusaba ,  Karen A. Nummy ,  Carl J. Radens ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/20

CPC分类号： H01L27/10823 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/66181

摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.

摘要翻译： 提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层 的沟槽。 在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。 在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。 掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。

公开(公告)号：US08053823B2

公开(公告)日：2011-11-08

申请号：US10906808

申请日：2005-03-08

申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Herbert L. Ho ,  Carl J. Radens

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Herbert L. Ho ,  Carl J. Radens

IPC分类号： H01L27/108

CPC分类号： H01L21/84 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： A structure is provided herein which includes an array of trench capacitors having at least portions disposed below a buried oxide layer of an SOI substrate. Each trench capacitor shares a common unitary buried capacitor plate which includes at least a portion of a first unitary semiconductor region disposed below the buried oxide layer. An upper boundary of the buried capacitor plate defines a plane parallel to a major surface of the substrate which extends laterally throughout the array of trench capacitors. In a particular embodiment, which starts from either an SOI or a bulk substrate, trenches of the array and a contact hole are formed simultaneously, such that the contact hole extends to substantially the same depth as the trenches. The contact hole preferably has substantially greater width than the trenches such that the conductive contact via can be formed simultaneously by processing used to form trench capacitors extending along walls of the trenches.

摘要翻译： 本文提供了一种结构，其包括具有设置在SOI衬底的掩埋氧化物层下方的至少部分的沟槽电容器阵列。 每个沟槽电容器共享共同的单一掩埋电容器板，其包括设置在掩埋氧化物层下方的第一单一半导体区域的至少一部分。 掩埋电容器板的上边界限定平行于衬底的主表面的平面，横向延伸穿过整个沟槽电容器阵列。 在从SOI或体衬底开始的特定实施例中，阵列的沟槽和接触孔同时形成，使得接触孔延伸到与沟槽基本相同的深度。 接触孔优选地具有比沟槽更大的宽度，使得可以通过用于形成沿着沟槽的壁延伸的沟槽电容器的处理同时形成导电接触通孔。

公开(公告)号：US20110092043A1

公开(公告)日：2011-04-21

申请号：US12974451

申请日：2010-12-21

申请人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

发明人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

IPC分类号： H01L21/02

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/1087

摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.

摘要翻译： 深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。 顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。 然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。 离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。 节点电介质和沟槽填充材料沉积到深沟槽中。 掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

公开(公告)号：US07807526B2

公开(公告)日：2010-10-05

申请号：US11928615

申请日：2007-10-30

申请人： Herbert L. Ho ,  Jack A. Mandelman ,  Tak H. Ning ,  Yoichi Otani

发明人： Herbert L. Ho ,  Jack A. Mandelman ,  Tak H. Ning ,  Yoichi Otani

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/7926

摘要： The present invention provides two-transistor silicon-oxide-nitride-oxide-semiconductor (2-Tr SONOS) non-volatile memory cells with randomly accessible storage locations as well as method of fabricating the same. In one embodiment, a 2-Tr SONOS cell is provided in which the select transistor is located with a trench structure having trench depth from 1 to 2 μm and the memory transistor is located on a surface of a semiconductor substrate adjoining the trench structure. In another embodiment, a 2-Tr SONOS memory cell is provided in which both the select transistor and the memory transistor are located within a trench structure having the depth mentioned above.

摘要翻译： 本发明提供具有随机存取的存储位置的双晶体管氧化硅 - 氧化物 - 氧化物半导体（2-Tr SONOS）非易失性存储单元及其制造方法。 在一个实施例中，提供了2-Tr SONOS单元，其中选择晶体管位于具有1至2μm的沟槽深度的沟槽结构，并且存储晶体管位于与沟槽结构相邻的半导体衬底的表面上。 在另一个实施例中，提供了2-Tr SONOS存储单元，其中选择晶体管和存储晶体管都位于具有上述深度的沟槽结构内。

公开(公告)号：US07763518B2

公开(公告)日：2010-07-27

申请号：US12099437

申请日：2008-04-08

申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

IPC分类号： H01L21/331

CPC分类号： H01L29/7317

摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

公开(公告)号：US20090184356A1

公开(公告)日：2009-07-23

申请号：US12016312

申请日：2008-01-18

申请人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

发明人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

IPC分类号： H01L29/94 ,  H01L21/20

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/1087

摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.

摘要翻译： 深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。 顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。 然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。 离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。 节点电介质和沟槽填充材料沉积到深沟槽中。 掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

公开(公告)号：US20090173980A1

公开(公告)日：2009-07-09

申请号：US11969989

申请日：2008-01-07

申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Herbert L. Ho ,  Paul C. Parries

发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Herbert L. Ho ,  Paul C. Parries

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/1087 ,  H01L27/10891

摘要： A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.

摘要翻译： 存储单元具有存取晶体管和具有设置在深沟槽内的电极的电容器。 STI氧化物覆盖电极的至少一部分，衬垫覆盖电极的剩余部分。 衬垫可以是一层氧化物上的氮化物层。 一些STI可以覆盖衬垫的一部分。 在存储器阵列中，可以通过STI氧化物和衬垫从电极隔离通过字线。

公开(公告)号：US20090158234A1

公开(公告)日：2009-06-18

申请号：US11955913

申请日：2007-12-13

申请人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

发明人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

IPC分类号： G06F17/50

CPC分类号： H01L29/42352 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

摘要： A semiconductor memory device and a design structure including the semiconductor memory device embodied in a machine readable medium is provided. In particular the present invention includes a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

摘要翻译： 提供半导体存储器件和包括体现在机器可读介质中的半导体存储器件的设计结构。 特别地，本发明包括其中在绝缘体上半导体（SOI）衬底中产生垂直沟槽半导体 - 氧化物 - 氮化物 - 氧化物 - 半导体（SONOS）存储单元的半导体存储器件，其允许将 基于SOI的互补金属氧化物半导体（CMOS）技术中的致密非易失性随机存取存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。