公开(公告)号：US07592265B2

公开(公告)日：2009-09-22

申请号：US11620028

申请日：2007-01-04

申请人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Min-Chieh Yang ,  Jiunn-Hsiung Liao

发明人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Min-Chieh Yang ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/28123 ,  H01L21/0271 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/7624 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/947 ,  Y10S438/95

摘要： A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.

摘要翻译： 提供了修剪硬掩模的方法。 该方法包括在衬底上提供衬底，硬掩模层和三层堆叠。 三层堆叠包括顶部光致抗蚀剂层，硅光致抗蚀剂层和底部光致抗蚀剂层。 顺序地对顶部光致抗蚀剂层，硅光致抗蚀剂层，底部光致抗蚀剂层和硬掩模层进行图案化。 在硬掩模层上进行修整处理。 本发明的底部光致抗蚀剂层在蚀刻工艺中更薄并且损失一些高度，因此底部光致抗蚀剂层将不会塌陷。

公开(公告)号：US20090206403A1

公开(公告)日：2009-08-20

申请号：US12430107

申请日：2009-04-27

申请人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Min-Chieh Yang ,  Jiunn-Hsiung Liao

发明人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Min-Chieh Yang ,  Jiunn-Hsiung Liao

IPC分类号： H01L29/06

CPC分类号： H01L21/28123 ,  H01L21/0271 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/7624 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/947 ,  Y10S438/95

摘要： A stack structure for forming a gate of a MOS transistor includes a substrate including a plurality of shallow trench isolations therein; a dielectric layer, a conductive layer and a hard mask layer formed on the substrate in sequence; and a tri-layer stack comprising a top photo resist layer, a silicon-containing photo resist layer and a bottom anti-reflective coating (BARC) on the hard mask layer, wherein the silicon-containing photo resist layer comprises 10-30% silicon and the hard mask layer has a high etching selectivity ratio to the conductive layer.

摘要翻译： 用于形成MOS晶体管的栅极的堆叠结构包括其中包括多个浅沟槽隔离的衬底; 依次形成在基板上的电介质层，导电层和硬掩模层; 以及包括在所述硬掩模层上的顶部光致抗蚀剂层，含硅光刻胶层和底部抗反射涂层（BARC）的三层堆叠，其中所述含硅光致抗蚀剂层包括10-30％的硅 并且硬掩模层与导电层具有高蚀刻选择性比。

公开(公告)号：US20090145877A1

公开(公告)日：2009-06-11

申请号：US12371809

申请日：2009-02-16

申请人： Feng-Yih Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

发明人： Feng-Yih Chang ,  Pei-Yu Chou ,  Jiunn-Hsiung Liao ,  Chih-Wen Feng ,  Ying-Chih Lin

IPC分类号： B44C1/22

CPC分类号： H01L21/76804 ,  H01L21/31144 ,  H01L21/76895

摘要： A method for controlling an ADI-AEI CD difference ratio of openings having different sizes is described. The openings are formed through a silicon-containing material layer, an etching resistive layer and a target material layer in turn. Before the opening etching steps, at least one of the opening patterns in the photoresist mask is altered in size through photoresist trimming or deposition of a substantially conformal polymer layer. A first etching step forming thicker polymer on the sidewall of the wider opening pattern is performed to form a patterned Si-containing material layer. A second etching step is performed to remove exposed portions of the etching resistive layer and the target material layer. At least one parameter among the parameters of the photoresist trimming or polymer layer deposition step and the etching parameters of the first etching step is controlled to obtain a predetermined ADI-AEI CD difference ratio.

摘要翻译： 描述了用于控制具有不同尺寸的开口的ADI-AEI CD差异比率的方法。 开口依次形成为含硅材料层，蚀刻电阻层和靶材料层。 在开口蚀刻步骤之前，光致抗蚀剂掩模中的至少一个开口图案的尺寸通过基本上保形的聚合物层的光致抗蚀剂修饰或沉积而改变。 执行在更宽的开口图案的侧壁上形成较厚聚合物的第一蚀刻步骤以形成图案化的含Si材料层。 执行第二蚀刻步骤以去除蚀刻电阻层和目标材料层的暴露部分。 控制光致抗蚀剂修整或聚合物层沉积步骤的参数中的至少一个参数和第一蚀刻步骤的蚀刻参数以获得预定的ADI-AEI CD差异比。

公开(公告)号：US07378341B2

公开(公告)日：2008-05-27

申请号：US11382060

申请日：2006-05-08

申请人： Pei-Yu Chou ,  Wen-Chou Tsai ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Wen-Chou Tsai ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/4763

CPC分类号： H01L21/31144 ,  H01L21/31116 ,  H01L21/76816 ,  H01L22/12

摘要： Automatic process control of after-etch-inspection critical dimension. A dielectric layer is deposited over a substrate and is then planarized to a first thickness. A cap oxide layer having a second thickness is deposited, wherein the combination of the first thickness and the second thickness is substantially constant. An ADI CD of a contact hole to be formed on the substrate is altered and pre-determined based on the second thickness of the cap oxide layer. A photoresist layer is formed on the cap oxide layer. An opening having the predetermined ADI CD is formed in the photoresist layer. Using the photoresist layer as an etching mask, the cap oxide layer and the dielectric layer is etched through the opening to form a contact hole having an AEI CD.

摘要翻译： 蚀刻后检测临界尺寸的自动过程控制。 介电层沉积在衬底上，然后被平坦化为第一厚度。 沉积具有第二厚度的帽氧化物层，其中第一厚度和第二厚度的组合基本上是恒定的。 要形成在基板上的接触孔的ADI CD根据盖氧化物层的第二厚度改变并预先确定。 在氧化膜层上形成光致抗蚀剂层。 具有预定ADI CD的开口形成在光致抗蚀剂层中。 使用光致抗蚀剂层作为蚀刻掩模，通过开口蚀刻帽氧化物层和电介质层，以形成具有AEI CD的接触孔。

公开(公告)号：US20070259527A1

公开(公告)日：2007-11-08

申请号：US11382060

申请日：2006-05-08

申请人： Pei-Yu Chou ,  Wen-Chou Tsai ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Wen-Chou Tsai ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/31116 ,  H01L21/76816 ,  H01L22/12

摘要： Automatic process control of after-etch-inspection critical dimension. A dielectric layer is deposited over a substrate and is then planarized to a first thickness. A cap oxide layer having a second thickness is deposited, wherein the combination of the first thickness and the second thickness is substantially constant. An ADI CD of a contact hole to be formed on the substrate is altered and pre-determined based on the second thickness of the cap oxide layer. A photoresist layer is formed on the cap oxide layer. An opening having the predetermined ADI CD is formed in the photoresist layer. Using the photoresist layer as an etching mask, the cap oxide layer and the dielectric layer is etched through the opening to form a contact hole having an AEI CD.

摘要翻译： 蚀刻后检测临界尺寸的自动过程控制。 介电层沉积在衬底上，然后被平坦化为第一厚度。 沉积具有第二厚度的帽氧化物层，其中第一厚度和第二厚度的组合基本上是恒定的。 要形成在基板上的接触孔的ADI CD根据盖氧化物层的第二厚度改变并预先确定。 在氧化膜层上形成光致抗蚀剂层。 具有预定ADI CD的开口形成在光致抗蚀剂层中。 使用光致抗蚀剂层作为蚀刻掩模，通过开口蚀刻帽氧化物层和电介质层，以形成具有AEI CD的接触孔。

公开(公告)号：US09196524B2

公开(公告)日：2015-11-24

申请号：US13609213

申请日：2012-09-10

申请人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Shang-Yuan Tsai

发明人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Shang-Yuan Tsai

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L21/76816 ,  H01L21/31144 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method of a semiconductor device is disclosed in the present invention. First, at least one gate structure and plurality of source/drain regions on a substrate are formed, a dielectric layer is then formed on the substrate, a first contact hole and a second contact hole are formed in the dielectric layer, respectively on the gate structure and the source/drain region, and a third contact hole is formed in the dielectric layer, wherein the third contact hole overlaps the first contact hole and the second contact hole.

摘要翻译： 在本发明中公开了一种半导体器件的制造方法。 首先，在衬底上形成至少一个栅极结构和多个源极/漏极区域，然后在衬底上形成电介质层，在电介质层中分别在栅极上形成第一接触孔和第二接触孔 结构和源极/漏极区，以及在电介质层中形成第三接触孔，其中第三接触孔与第一接触孔和第二接触孔重叠。

公开(公告)号：US08691659B2

公开(公告)日：2014-04-08

申请号：US13281459

申请日：2011-10-26

申请人： Ching-Pin Hsu ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Shang-Yuan Tsai ,  Li-Chiang Chen

发明人： Ching-Pin Hsu ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Shang-Yuan Tsai ,  Li-Chiang Chen

IPC分类号： H01L21/762

CPC分类号： H01L21/76232

摘要： A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.

摘要翻译： 公开了一种形成没有空隙的电介质层的方法。 首先，提供基板，包括凹部的第一应力层，设置在第一应力层上并覆盖凹部的第二应力层和嵌入凹部中的图案化光致抗蚀剂。 第二，执行第一蚀刻步骤以完全去除光致抗蚀剂，使得剩余的第二应力层形成邻近凹部的至少一个突起。 然后，在不暴露的情况下形成修整光致抗蚀剂以填充凹部并覆盖突起。 然后，进行修整蚀刻步骤以消除突起并且顺利地移除修整光致抗蚀剂。

公开(公告)号：US08592321B2

公开(公告)日：2013-11-26

申请号：US13156319

申请日：2011-06-08

申请人： Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

发明人： Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

IPC分类号： H01L21/46 ,  H01L21/302

CPC分类号： H01L21/308 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816

摘要： A method for fabricating an aperture is disclosed. The method includes the steps of: forming a hard mask containing carbon on a surface of a semiconductor substrate; and using a non-oxygen element containing gas to perform a first etching process for forming a first aperture in the hard mask.

摘要翻译： 公开了一种制造孔的方法。 该方法包括以下步骤：在半导体衬底的表面上形成含有碳的硬掩模; 并且使用含有气体的非氧元素进行用于在硬掩模中形成第一孔的第一蚀刻工艺。

公开(公告)号：US08574990B2

公开(公告)日：2013-11-05

申请号：US13033616

申请日：2011-02-24

申请人： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Shui-Yen Lu ,  Pei-Yu Chou ,  Shin-Chi Chen ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chan-Lon Yang ,  Teng-Chun Tsai ,  Chun-Hsien Lin

发明人： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Shui-Yen Lu ,  Pei-Yu Chou ,  Shin-Chi Chen ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chan-Lon Yang ,  Teng-Chun Tsai ,  Chun-Hsien Lin

IPC分类号： H01L21/00

CPC分类号： H01L29/66545 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4966

摘要： The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened.

摘要翻译： 本发明提供一种制造具有金属栅极的半导体器件的方法。 首先，提供基板。 具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。 去除第一牺牲栅极以形成第一沟槽，然后在第一沟槽中形成第一金属层和第一材料层。 接下来，第一金属层和第一材料层变平。 去除第二牺牲栅极以形成第二沟槽，然后在第二沟槽中形成第二金属层和第二材料层。 最后，第二金属层和第二材料层变平。

公开(公告)号：US20130093062A1

公开(公告)日：2013-04-18

申请号：US13276306

申请日：2011-10-18

申请人： Ying-Chih Lin ,  Hsuan-Hsu Chen ,  Jiunn-Hsiung Liao ,  Lung-En Kuo

发明人： Ying-Chih Lin ,  Hsuan-Hsu Chen ,  Jiunn-Hsiung Liao ,  Lung-En Kuo

IPC分类号： H01L29/02 ,  H01L21/302

CPC分类号： H01L21/311 ,  H01L21/3083 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.

摘要翻译： 半导体结构包括基板，凹部和材料。 凹部位于基板中，其中凹部具有上部和下部。 上部的最小宽度大于下部的最大宽度。 材料位于凹槽中。