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292 条记录 (耗时 0.037 秒)

    Transistors with metal gate and methods for forming the same
    62.
    发明授权
    Transistors with metal gate and methods for forming the same 有权
    具有金属栅极的晶体管及其形成方法

    公开(公告)号：US08198685B2

    公开(公告)日：2012-06-12

    申请号：US12343307

    申请日：2008-12-23

    申请人： Chung-Shi Liu ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

    IPC分类号： H01L27/092 ,  H01L21/28

    CPC分类号： H01L29/517 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513

    摘要： A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MCxOy) containing layer is formed over the at least one first gate dielectric layer, wherein the transition-metal (M) has an atomic percentage of about 40 at. % or more. A first gate is formed over the first transition-metal oxycarbide containing layer. At least one first doped region is formed within the substrate and adjacent to a sidewall of the first gate.

    摘要翻译： 半导体器件包括在衬底上的至少一个第一栅极电介质层。 在所述至少一个第一栅极介电层上形成含有第一过渡金属碳氧化物（MCxOy）的层，其中所述过渡金属（M）的原子百分比为约40原子。 ％ 或者更多。 在第一过渡金属含碳氧化物层上形成第一栅极。 至少一个第一掺杂区域形成在衬底内并且邻近第一栅极的侧壁。

    Self-aligned air-gap in interconnect structures
    64.
    发明申请
    Self-aligned air-gap in interconnect structures 有权
    互连结构中的自对准气隙

    公开(公告)号：US20080182405A1

    公开(公告)日：2008-07-31

    申请号：US11698565

    申请日：2007-01-26

    申请人： Chung-Shi Liu ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Chen-Hua Yu

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit structure comprising an air gap and methods for forming the same are provided. The integrated circuit structure includes a conductive line; a self-aligned dielectric layer on a sidewall of the conductive line; an air-gap horizontally adjoining the self-aligned dielectric layer; a low-k dielectric layer horizontally adjoining the air-gap; and a dielectric layer on the air-gap and the low-k dielectric layer.

    摘要翻译： 提供一种包括气隙的集成电路结构及其形成方法。 集成电路结构包括导线; 在导电线的侧壁上的自对准电介质层; 水平地邻接所述自对准介电层的气隙; 水平地邻接气隙的低k电介质层; 以及气隙和低k电介质层上的电介质层。

    Via recess in underlying conductive line
    65.
    发明授权
    Via recess in underlying conductive line 有权
    通过下面的导电线路中的凹槽

    公开(公告)号：US07180193B2

    公开(公告)日：2007-02-20

    申请号：US10823159

    申请日：2004-04-13

    申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Horng-Huei Tseng

    发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Horng-Huei Tseng

    IPC分类号： H01L23/522

    CPC分类号： H01L23/5329 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a dielectric layer, a conductive line, a via, and a via recess in the conductive line. The conductive line is underlying the dielectric layer. The via is formed in the dielectric layer and extends into the conductive line to form the via recess in the conductive line. The via recess formed in the conductive line has a depth of at least about 100 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example.

    摘要翻译： 半导体器件包括导电线中的电介质层，导电线，通孔和通路凹槽。 导电线在电介质层的下面。 通孔形成在电介质层中并延伸到导电线中以在导电线中形成通路凹槽。 形成在导电线中的通路凹槽具有至少约100埃的深度。 通孔填充材料填充通孔凹部并且至少部分地填充通孔，使得通孔填充材料电连接到导电线。 例如，通孔凹部可以具有与通孔相同的尺寸或更小的横截面面积。 例如，这种通孔结构可以是金属间电介质结构中的双镶嵌结构的一部分。

    Via recess in underlying conductive line
    66.
    发明申请
    Via recess in underlying conductive line 有权
    通过下面的导电线路中的凹槽

    公开(公告)号：US20050224855A1

    公开(公告)日：2005-10-13

    申请号：US10823159

    申请日：2004-04-13

    申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Horng-Huei Tseng

    发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Horng-Huei Tseng

    IPC分类号： G03G15/16 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    CPC分类号： H01L23/5329 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a dielectric layer, a conductive line, a via, and a via recess in the conductive line. The conductive line is underlying the dielectric layer. The via is formed in the dielectric layer and extends into the conductive line to form the via recess in the conductive line. The via recess formed in the conductive line has a depth of at least about 100 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example.

    摘要翻译： 半导体器件包括导电线中的电介质层，导电线，通孔和通路凹槽。 导电线在电介质层的下面。 通孔形成在电介质层中并延伸到导电线中以在导电线中形成通路凹槽。 形成在导电线中的通路凹槽具有至少约100埃的深度。 通孔填充材料填充通孔凹部并且至少部分地填充通孔，使得通孔填充材料电连接到导电线。 例如，通孔凹部可以具有与通孔相同的尺寸或更小的横截面面积。 例如，这种通孔结构可以是金属间电介质结构中的双镶嵌结构的一部分。

    Tungsten-copper interconnect and method for fabricating the same
    67.
    发明申请
    Tungsten-copper interconnect and method for fabricating the same 审中-公开
    钨铜互连及其制造方法

    公开(公告)号：US20050064629A1

    公开(公告)日：2005-03-24

    申请号：US10665309

    申请日：2003-09-22

    申请人： Chen-Hua Yu ,  Tsu Shih ,  Chung-Shi Liu ,  Shwang-Min Jeng ,  Horng-Huei Tseng

    发明人： Chen-Hua Yu ,  Tsu Shih ,  Chung-Shi Liu ,  Shwang-Min Jeng ,  Horng-Huei Tseng

    IPC分类号： H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/76829 ,  H01L21/76834

    摘要： An interconnect structure utilizing a silicon carbon-containing film as an interlayer between dielectrics. A semiconductor substrate having a conductor thereon is provided, and an insulating layer overlies the semiconductor substrate. The insulating layer has a via hole therein to expose the conductor. A conductive plug, e.g. a tungsten plug, substantially fills the via hole and electrically connects the underlying conductor. A silicon carbon-containing film and a low k dielectric layer overlie the insulating layer and the conductive plug, and have a trench therein exposing the conductive plug. A copper or copper alloy conductor substantially fills the trench.

    摘要翻译： 利用含硅碳膜作为电介质之间的中间层的互连结构。 设置有其上具有导体的半导体衬底，并且绝缘层覆盖在半导体衬底上。 绝缘层在其中具有通孔以露出导体。 导电塞，例如。 钨插头基本上填充通孔并电连接下面的导体。 含硅碳膜和低k电介质层覆盖在绝缘层和导电插塞上，并且在其中具有暴露导电插塞的沟槽。 铜或铜合金导体基本上填充沟槽。

    Passivation method for copper process
    69.
    发明授权
    Passivation method for copper process 有权
    铜工艺钝化方法

    公开(公告)号：US06424021B1

    公开(公告)日：2002-07-23

    申请号：US09607285

    申请日：2000-06-30

    申请人： Chung-Shi Liu ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Chen-Hua Yu

    IPC分类号： H01L2358

    CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A composite dielectric layer and method of forming the composite dielectric layer for the passivation of exposed copper in a copper damascene structure are described. The composite layer consists of a passivation dielectric layer and an etch stop dielectric layer and is formed over the exposed copper prior to the deposit of an inter-metal or final passivating dielectric layer. Via holes are etched in the inter-metal or final passivating layer and the composite dielectric layer provides an etch stop function as well as passivation for the exposed copper conductor. A thin layer of passivation dielectric, such as silicon nitride, is formed directly over the exposed copper to passivate the copper. A thin layer of etch stop dielectric, such as silicon oxynitride, is then formed over the layer of passivation dielectric. The passivation dielectric is chosen for passivation properties and adhesion between the passivation dielectric and copper. The etch stop layer is chosen for etch stop properties. The composite layer is thinner than would be required if the layer of passivation dielectric also provided the etch stop function so that circuit capacitance is reduced by using the composite layer.

    摘要翻译： 描述了复合电介质层和形成用于钝化铜镶嵌结构中的暴露铜的复合介电层的方法。 复合层由钝化电介质层和蚀刻停止介电层组成，并且在沉积金属间或最后的钝化介电层之前形成在暴露的铜上。 在金属间或最后的钝化层中蚀刻通孔，并且复合介电层为暴露的铜导体提供蚀刻停止功能以及钝化。 钝化电介质（例如氮化硅）的薄层直接形成在暴露的铜上以钝化铜。 然后在钝化电介质层上形成薄层的蚀刻停止电介质，例如氮氧化硅。 选择钝化电介质用于钝化性能和钝化电介质和铜之间的粘附。 选择蚀刻停止层用于蚀刻停止性质。 如果钝化电介质层还提供蚀刻停止功能，则复合层比所需要的薄，以便通过使用复合层减少电路电容。

    Effective diffusion barrier
    70.
    发明授权
    Effective diffusion barrier 有权
    有效的扩散屏障

    公开(公告)号：US06353260B2

    公开(公告)日：2002-03-05

    申请号：US09785106

    申请日：2001-02-20

    申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L2348

    CPC分类号： H01L21/76856 ,  H01L21/76805 ,  H01L21/76843

    摘要： In forming a semiconductor device in which an electrically conductive substrate is covered with a dielectric layer by the following steps, form a trench with a trench line on top and a contact hole on the bottom in the dielectric layer with the overall trench reaching down to the substrate. Preclean the trench. Form a tantalum film over the dielectric layer including the trench walls, covering the exposed the substrate surface. Fill grain boundaries of the tantalum film with at least one of tantalum oxide and tantalum nitride forming a filled tantalum film. Form a redeposited tantalum layer above the filled tantalum film. Form a copper seed film above the redeposited tantalum film. Plate the device filling the trench with a plated bulk copper layer on the seed film. Planarize the device to expose the top surface of the dielectric layer, removing surplus portions of the filled tantalum film, the copper seed film, and the bulk copper layer. The filled tantalum film is formed by exposing the tantalum to air under STP atmospheric conditions or by exposure to a nitrous oxide (N2O) gas in a plasma at a temperature of about 400° C.

    摘要翻译： 在通过以下步骤形成其中导电基板被电介质层覆盖的半导体器件中，在电介质层的顶部形成有沟槽线的沟槽和底部的接触孔，其中整个沟槽到达 基质。 清洁沟槽。 在包括沟槽壁的电介质层上形成钽膜，覆盖暴露的衬底表面。 用钽氧化物和氮化钽中的至少一种填充钽膜的晶界，形成填充的钽膜。 在填充的钽膜上方形成再沉积的钽层。 在再沉积的钽膜上方形成铜籽晶膜。 将装有填充沟槽的装置用种子膜上的电镀体铜层铺平。 平面化器件以暴露电介质层的顶表面，去除填充的钽膜，铜籽晶膜和块状铜层的剩余部分。 填充的钽膜通过在STP大气条件下暴露于空气或通过在约400℃的温度下暴露于等离子体中的一氧化二氮（N 2 O）气体而形成。