公开(公告)号：US20090303774A1

公开(公告)日：2009-12-10

申请号：US12511846

申请日：2009-07-29

申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C17/165 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0069 ,  G11C17/16 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/77

摘要： A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f)R. The logic “1” state is represented by a mathematical expression (n+f)R. The logic “2” state is represented by a mathematical expression (1+nf)R. The logic “3” state is represented by a mathematical expression n(1+f)R.

摘要翻译： 描述了一种用于操作具有串联排列的两个存储层堆叠的双稳态电阻随机存取存储器的方法。 双稳态电阻随机存取存储器包括每个存储单元的两个存储层堆栈，双稳态电阻随机存取存储器以四个逻辑状态，逻辑“00”状态，逻辑“01”状态，逻辑“10”状态和逻辑 “11”状态。 四个不同逻辑状态之间的关系可以由两个变量n和f以及电阻R在数学上表示。逻辑“0”状态由数学表达式（1 + f）R表示。 逻辑“1”状态由数学表达式（n + f）R表示。 逻辑“2”状态由数学表达式（1 + nf）R表示。 逻辑“3”状态由数学表达式n（1 + f）R表示。

公开(公告)号：US07616472B2

公开(公告)日：2009-11-10

申请号：US11552032

申请日：2006-10-23

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/122 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1633

摘要： A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer.

摘要翻译： 可选择地显示第一和第二逻辑电平的存储器件。 第一导电材料具有形成在其上的第一存储层的第一表面，并且第二导电材料具有形成在其上的第二存储层的第二表面。 连接导电层连接第一和第二存储层并将其放置在电接触中。 该结构被设计成使得第一存储层的横截面积小于第二存储层的横截面面积。

公开(公告)号：US07586778B2

公开(公告)日：2009-09-08

申请号：US12134117

申请日：2008-06-05

申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C17/165 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0069 ,  G11C17/16 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/77

摘要： A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f) R. The logic “1” state is represented by a mathematical expression (n+f) R. The logic “2” state is represented by a mathematical expression (1+nf) R. The logic “3” state is represented by a mathematical expression n(1+f) R.

摘要翻译： 描述了一种用于操作具有串联排列的两个存储层堆叠的双稳态电阻随机存取存储器的方法。 双稳态电阻随机存取存储器包括每个存储单元的两个存储层堆栈，双稳态电阻随机存取存储器以四个逻辑状态，逻辑“00”状态，逻辑“01”状态，逻辑“10”状态和逻辑 “11”状态。 四个不同逻辑状态之间的关系可以用两个变量n和f以及电阻R在数学上表示。逻辑“0”状态由数学表达式（1 + f）R 逻辑“1”状态由数学表达式（n + f）R表示。逻辑“2”状态由数学表达式（1 + nf）R表示。逻辑“3”状态由数学 表达式n（1 + f）R

公开(公告)号：US07531825B2

公开(公告)日：2009-05-12

申请号：US11463824

申请日：2006-08-10

申请人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L47/00 ,  G11C11/56

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1683

摘要： A non-volatile method with a self-aligned RRAM element. The method includes a lower electrode element, generally planar in form, having an inner contact surface. At the top of the device is a upper electrode element, spaced from the lower electrode element. A containment structure extends between the upper electrode element and the lower electrode element, and this element includes a sidewall spacer element having an inner surface defining a generally funnel-shaped central cavity, terminating at a terminal edge to define a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode, having an inner surface defining a thermal isolation cell, the spandrel inner walls being spaced radially outward from the sidewall spacer terminal edge, such that the sidewall spacer terminal edge projects radially inward from the spandrel element inner surface. ARRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element.

摘要翻译： 具有自对准RRAM元素的非易失性方法。 该方法包括具有内部接触表面的大体平面形状的下部电极元件。 在装置的顶部是与下部电极元件间隔开的上部电极元件。 容纳结构在上电极元件和下电极元件之间延伸，并且该元件包括侧壁间隔元件，其具有限定大致漏斗形中心腔的内表面，终止于端边缘以限定中心孔; 以及位于所述侧壁间隔元件和所述下电极之间的突出元件，具有限定了热隔离单元的内表面，所述凸起内壁与所述侧壁间隔件终端边缘径向向外间隔开，使得所述侧壁间隔件末端边缘径向向内突出 从弹簧元件内表面。 ARRAM元件在下电极元件和上电极之间延伸，占据侧壁间隔元件中心空腔的至少一部分并且从侧壁间隔件终端边缘朝向和与下电极接触。 以这种方式，伞形元件内表面与RRAM元件间隔开以限定与RRAM元件相邻的热隔离单元。

公开(公告)号：US20090020746A1

公开(公告)日：2009-01-22

申请号：US12235773

申请日：2008-09-23

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

IPC分类号： H01L45/00

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

摘要翻译： 制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。 该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料， 选择性材料。 柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。 可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

公开(公告)号：US07468299B2

公开(公告)日：2008-12-23

申请号：US11197659

申请日：2005-08-04

申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Hang-Ting Lue

发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Hang-Ting Lue

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： Methods for forming non-volatile memory cells include: (a) providing a semiconductor substrate having at least two source/drain regions, and a dielectric material disposed on the substrate above at least one of the at least two source/drain regions wherein the dielectric material has an exposed surface, and wherein the at least two source/drain regions are separated by a recess trench having an exposed surface, wherein the trench extends downward into the substrate to a depth position below the at least two source/drain regions; (b) forming a charge-trapping layer on the exposed surfaces of the dielectric material and the recess trench; and (c) forming a gate above the charge-trapping layer.

摘要翻译： 用于形成非易失性存储单元的方法包括：（a）提供具有至少两个源极/漏极区域的半导体衬底和设置在至少两个源极/漏极区域中的至少一个的衬底上的电介质材料，其中电介质 材料具有暴露的表面，并且其中所述至少两个源极/漏极区域被具有暴露表面的凹槽分隔开，其中所述沟槽向下延伸到所述衬底中至所述至少两个源极/漏极区域下方的深度位置; （b）在电介质材料和凹槽沟的暴露表面上形成电荷捕获层; 和（c）在电荷俘获层上形成栅极。

公开(公告)号：US07414282B2

公开(公告)日：2008-08-19

申请号：US11203087

申请日：2005-08-15

申请人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

摘要翻译： 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅极上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

公开(公告)号：US20080173982A1

公开(公告)日：2008-07-24

申请号：US11656246

申请日：2007-01-18

申请人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang-Yeu Hsieh

发明人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/12

CPC分类号： H01L27/24 ,  G11C11/5664 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0016 ,  G11C16/0475 ,  G11C2213/31 ,  G11C2213/51

摘要： A memory comprises a number of word lines in a first direction, a number of bit lines in a second direction, each coupled to at least one of the word lines, and a number of memory elements, each coupled to one of the word lines and one of the bit lines. Each memory element comprises a top electrode for connecting to a corresponding word line, a bottom electrode for connecting to a corresponding bit line, a resistive layer on the bottom electrode, and at least two separate liners, each liner having resistive materials on both ends of the liner and each liner coupled between the top electrode and the resistive layer.

摘要翻译： 存储器包括在第一方向上的多个字线，第二方向上的多个位线，每个字线连接到至少一个字线，以及多个存储器元件，每个存储器元件耦合到字线之一， 其中一个位线。 每个存储元件包括用于连接到对应的字线的顶部电极，用于连接到对应的位线的底部电极，底部电极上的电阻层，以及至少两个分离的衬垫，每个衬垫在两端具有电阻材料 衬垫和每个衬垫耦合在顶部电极和电阻层之间。

公开(公告)号：US20080121861A1

公开(公告)日：2008-05-29

申请号：US11465094

申请日：2006-08-16

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

IPC分类号： H01L45/00

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

摘要翻译： 制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。 该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料， 选择性材料。 柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。 可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

公开(公告)号：US08482052B2

公开(公告)日：2013-07-09

申请号：US12056489

申请日：2008-03-27

申请人： Hang-Ting Lue ,  Erh-Kun Lai

发明人： Hang-Ting Lue ,  Erh-Kun Lai

IPC分类号： H01L29/792 ,  H01L29/788

CPC分类号： H01L29/66833 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792

摘要： Thin film transistor memory cells are stackable, and employ bandgap engineered tunneling layers in a junction free, NAND configuration, that can be arranged in 3D arrays. The memory cells have a channel region in a semiconductor strip formed on an insulating layer, a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure having a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region, a charge storage layer disposed above the tunnel dielectric structure, an insulating layer disposed above the charge storage layer, and a gate electrode disposed above the insulating layer.

摘要翻译： 薄膜晶体管存储单元是可堆叠的，并且采用无结构的NAND配置的带隙工程隧道层，其可以排列成3D阵列。 所述存储单元具有在绝缘层上形成的半导体条中的沟道区，设置在所述沟道区上方的隧道电介质结构，所述隧道电介质结构具有多层结构，所述多层结构包括至少一层具有低于空穴穿透势垒高度的层。 在与沟道区域的界面处，设置在隧道介电结构上方的电荷存储层，设置在电荷存储层上方的绝缘层和设置在绝缘层上方的栅电极。