公开(公告)号：US08243494B2

公开(公告)日：2012-08-14

申请号：US12235773

申请日：2008-09-23

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

IPC分类号： G11C16/02 ,  H01L29/417

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

摘要翻译： 制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。 该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料， 选择性材料。 柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。 可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

公开(公告)号：US08178405B2

公开(公告)日：2012-05-15

申请号：US12755897

申请日：2010-04-07

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L21/8242

CPC分类号： H01L45/122 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1683

摘要： A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film.

摘要翻译： 存储单元装置具有底部电极和顶部电极，与底部电极接触的存储器材料的插头以及具有接触顶部电极的边缘和接触存储器的底部开口的杯形导电构件 材料。 因此，存储单元中的导电路径从顶部电极通过导电杯状构件，并通过相变材料的塞子到达底部电极。 此外，用于制造存储单元器件的方法包括在底部电极上形成包括绝缘元件和止动元件的底部电极岛的步骤，形成围绕岛的分离层，去除止动元件以在绝缘元件上方形成孔 在分离层中，在孔中形成导电膜，在导电膜上形成绝缘衬垫，进行蚀刻以形成具有边缘的杯形导电膜，并且通过绝缘衬垫和杯状导电体的底部形成开口 在底部电极的表面形成薄膜，在开口中形成相变记忆材料塞，形成与杯状导电膜的边缘接触的顶部电极。

公开(公告)号：US08139393B2

公开(公告)日：2012-03-20

申请号：US12576212

申请日：2009-10-08

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/122 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1633

摘要： A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer.

摘要翻译： 可选择地显示第一和第二逻辑电平的存储器件。 第一导电材料具有形成在其上的第一存储层的第一表面，并且第二导电材料具有形成在其上的第二存储层的第二表面。 连接导电层连接第一和第二存储层并将其放置在电接触中。 该结构被设计成使得第一存储层的横截面积小于第二存储层的横截面面积。

公开(公告)号：US07972893B2

公开(公告)日：2011-07-05

申请号：US12469184

申请日：2009-05-20

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang-Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/00

CPC分类号： H01L45/1226 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： A method for making a memory device includes providing a dielectric material, having first and second upwardly and inwardly tapering surfaces and a surface segment connecting the first and second surfaces. First and second electrodes are formed over the first and second surfaces. A memory element is formed over the surface segment to electrically connect the first and second electrodes.

摘要翻译： 制造存储器件的方法包括提供具有第一和第二向上和向内渐缩的表面的电介质材料以及连接第一和第二表面的表面段。 第一和第二电极形成在第一和第二表面上。 存储元件形成在表面段上以电连接第一和第二电极。

公开(公告)号：US07923285B2

公开(公告)日：2011-04-12

申请号：US12351692

申请日：2009-01-09

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L21/00

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1683

摘要： A non-volatile memory with a self-aligned RRAM element includes a lower electrode element, generally planar in form, having an inner contact surface; an upper electrode element, spaced from the lower electrode element; a containment structure extends between the upper electrode element and the lower electrode element, with a sidewall spacer element having a generally funnel-shaped central cavity with a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode. A RRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element.

摘要翻译： 具有自对准RRAM元件的非易失性存储器包括具有内接触表面的大体平面形状的下电极元件; 与所述下电极元件间隔开的上电极元件; 容纳结构在上电极元件和下电极元件之间延伸，侧壁间隔元件具有大致漏斗形的具有中心孔的中心腔; 以及位于侧壁间隔元件和下电极之间的突出元件。 RRAM元件在下电极元件和上电极之间延伸，占据侧壁间隔件元件中心腔的至少一部分并且从侧壁间隔件端子边缘朝向和与下电极接触。 以这种方式，伞形元件内表面与RRAM元件间隔开以限定与RRAM元件相邻的热隔离单元。

公开(公告)号：US07599217B2

公开(公告)日：2009-10-06

申请号：US11357902

申请日：2006-02-17

申请人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1691

摘要： A memory cell device, having a memory material switchable between electrical property states by the application of energy, comprises an electrode, a separation layer against an electrode surface, a hole in the separation layer, a second material in the hole defining a void having a downwardly and inwardly tapering void region. A memory material is in the void region in electrical contact with the electrode surface. A second electrode is in electrical contact with the memory material. Energy passing between the first and second electrodes is concentrated within the memory material so to facilitate changing an electrical property state of the memory material. The memory material may comprise a phase change material. The second material may comprise a high density plasma-deposited material. A method for making a memory cell device is also discussed.

摘要翻译： 具有可通过施加能量在电性能状态之间切换的记忆材料的存储单元装置包括电极，与电极表面相对的分离层，分离层中的孔，孔中的第二材料限定具有 向下和向内逐渐变细的空隙区域。 记忆材料位于与电极表面电接触的空隙区域中。 第二电极与记忆材料电接触。 在第一和第二电极之间的能量通过集中在存储材料内，以便于改变存储材料的电性能状态。 记忆材料可以包括相变材料。 第二材料可以包括高密度等离子体沉积材料。 还讨论了制造存储单元器件的方法。

公开(公告)号：US20090239358A1

公开(公告)日：2009-09-24

申请号：US12469184

申请日：2009-05-20

申请人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L21/28

CPC分类号： H01L45/1226 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： A method for making a memory device includes providing a dielectric material, having first and second upwardly and inwardly tapering surfaces and a surface segment connecting the first and second surfaces. First and second electrodes are formed over the first and second surfaces. A memory element is formed over the surface segment to electrically connect the first and second electrodes.

摘要翻译： 制造存储器件的方法包括提供具有第一和第二向上和向内渐缩的表面的电介质材料以及连接第一和第二表面的表面段。 第一和第二电极形成在第一和第二表面上。 存储元件形成在表面段上以电连接第一和第二电极。

公开(公告)号：US08111541B2

公开(公告)日：2012-02-07

申请号：US12715888

申请日：2010-03-02

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C13/0016 ,  G11C11/5664 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0014 ,  H01L45/04 ,  H01L45/124 ,  H01L45/146 ,  H01L45/1633

摘要： A method and structure of a bistable resistance random access memory comprise a plurality of programmable resistance random access memory cells where each programmable resistance random access memory cell includes multiple memory members for performing multiple bits for each memory cell. The bistable RRAM includes a first resistance random access member connected to a second resistance random access member through interconnect metal liners and metal oxide strips. The first resistance random access member has a first resistance value Ra, which is determined from the thickness of the first resistance random access member based on the deposition of the first resistance random access member. The second resistance random access member has a second resistance value Rb, which is determined from the thickness of the second resistance random access member based on the deposition of the second resistance random access member.

摘要翻译： 双稳态电阻随机存取存储器的方法和结构包括多个可编程电阻随机存取存储单元，其中每个可编程电阻随机存取存储单元包括用于为每个存储单元执行多位的多个存储器构件。 双稳态RRAM包括通过互连金属衬垫和金属氧化物条连接到第二电阻随机存取构件的第一电阻随机存取构件。 第一电阻随机存取构件具有基于第一电阻随机存取构件的沉积从第一电阻随机存取构件的厚度确定的第一电阻值Ra。 第二电阻随机存取部件具有基于第二电阻随机存取部件的沉积从第二电阻随机存取部件的厚度确定的第二电阻值Rb。

公开(公告)号：US08039392B2

公开(公告)日：2011-10-18

申请号：US12889229

申请日：2010-09-23

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L21/44

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1675 ,  Y10S438/90

摘要： A memory device has a sidewall insulating member with a sidewall insulating member length according to a first spacer layer thickness. A first electrode formed from a second spacer layer having a first electrode length according to a thickness of a second spacer layer and a second electrode formed from the second spacer layer having a second electrode length according to the thickness of the second spacer layer are formed on sidewalls of the sidewall insulating member. A bridge of memory material having a bridge width extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall insulating member, wherein the bridge comprises memory material.

摘要翻译： 存储器件具有侧壁绝缘构件，其具有根据第一间隔层厚度的侧壁绝缘构件长度。 由具有根据第二间隔层的厚度的第一电极长度和根据第二间隔层的厚度具有第二电极长度的由第二间隔层形成的第二电极的第二间隔层形成的第一电极形成在 侧壁绝缘部件的侧壁。 具有桥接宽度的记忆材料桥由第一电极的顶表面延伸穿过侧壁绝缘构件的顶表面延伸到第二电极的顶表面，其中桥包括记忆材料。

公开(公告)号：US07924600B2

公开(公告)日：2011-04-12

申请号：US12511846

申请日：2009-07-29

申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C17/165 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0069 ,  G11C17/16 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/77

摘要： A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f)R. The logic “1” state is represented by a mathematical expression (n+f)R. The logic “2” state is represented by a mathematical expression (1+nf)R. The logic “3” state is represented by a mathematical expression n(1+f)R.

摘要翻译： 描述了一种用于操作具有串联排列的两个存储层堆叠的双稳态电阻随机存取存储器的方法。 双稳态电阻随机存取存储器包括每个存储单元的两个存储层堆栈，双稳态电阻随机存取存储器以四个逻辑状态，逻辑“00”状态，逻辑“01”状态，逻辑“10”状态和逻辑 “11”状态。 四个不同逻辑状态之间的关系可以由两个变量n和f以及电阻R在数学上表示。逻辑“0”状态由数学表达式（1 + f）R表示。 逻辑“1”状态由数学表达式（n + f）R表示。 逻辑“2”状态由数学表达式（1 + nf）R表示。 逻辑“3”状态由数学表达式n（1 + f）R表示。