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公开(公告)号：US09362684B2
公开(公告)日：2016-06-07
申请号：US13997096
申请日：2011-12-14
CPC分类号： H01R24/64 , H01R12/721 , H01R13/66 , H01R13/6658 , H01R24/28 , H01R24/62 , H01R2107/00
摘要： Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.
摘要翻译： 方法和系统可以包括具有集成缓冲器的输入/输出（IO）接口，壳体和设置在壳体内的基板。 衬底可以包括第一侧，第二侧和连接边缘。 集成缓冲器可以耦合到衬底的第一侧和第二侧中的至少一个。 多个触点列可以耦合到衬底的第一侧。 每排触点可以基本上平行于连接边缘堆叠。 衬底可以具有耦合到其上的功率输出，并且集成缓冲器可以包括具有耦合到功率输出的电源输出的电压调节器。
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公开(公告)号：US20140237142A1
公开(公告)日：2014-08-21
申请号：US13995590
申请日：2011-09-30
CPC分类号： H04L41/0896 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more device-side data lanes and transceiver logic to receive a bandwidth configuration command. The transceiver logic may also configure a transmit bandwidth of the one or more device-side data lanes based on the bandwidth configuration command. Additionally, the transceiver logic can configure a receive bandwidth of the one or more device-side data lanes based on the bandwidth configuration command.
摘要翻译： 互连设备的系统和方法可以包括具有一个或多个设备侧数据通道的输入/输出（IO）接口和用于接收带宽配置命令的收发机逻辑。 收发器逻辑还可以基于带宽配置命令来配置一个或多个设备侧数据通道的发送带宽。 此外，收发器逻辑可以基于带宽配置命令来配置一个或多个设备侧数据通道的接收带宽。
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公开(公告)号：US08612809B2
公开(公告)日：2013-12-17
申请号：US12655590
申请日：2009-12-31
申请人： Bryan Casper , Randy Mooney , Dave Dunning , Mozhgan Mansuri , James E. Jaussi
发明人： Bryan Casper , Randy Mooney , Dave Dunning , Mozhgan Mansuri , James E. Jaussi
IPC分类号： G06F11/00 , G06F11/10 , G06F12/08 , G01R31/3177 , G06F11/25 , H03M13/05 , H03M13/15 , G11C5/02
CPC分类号： G06F11/1076 , G11C5/02 , G11C29/12 , H01L2224/16145 , H03M13/15 , H03M13/152
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
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64.发明授权公开(公告)号：US07529296B2
公开(公告)日：2009-05-05
申请号：US11232492
申请日：2005-09-21
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L2025/03598 , H04L2025/03681
摘要： In some embodiments disclosed herein, equalizers in a receiver are adapted during normal operation, as they extract bit data from a received bit stream, to account for channel and/or circuit fluctuations.
摘要翻译： 在本文公开的一些实施例中，接收机中的均衡器在正常操作期间被适配，因为它们从接收到的比特流中提取比特数据，以解决信道和/或电路波动。
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公开(公告)号：US20090086871A1
公开(公告)日：2009-04-02
申请号：US11905080
申请日：2007-09-27
IPC分类号： H04L7/00
CPC分类号： G01R31/31727 , G01R31/31726 , H03B5/1212 , H03B5/1228 , H03B5/1265 , H03B2200/0074 , H03L7/06 , H03L7/24 , H04L7/0008 , H04L7/0091 , H04L25/0272
摘要： An apparatus is provided that includes an injection locked oscillator and a transmitting device. The injection locked oscillator to receive a first clock signal and to provide a second clock signal by skewing the first clock signal. The transmitting device to receive an input signal and to receive the second clock signal as a clocking signal, the transmitting device to transmit an output signal based on the received clocking signal.
摘要翻译： 提供一种包括注入锁定振荡器和发送装置的装置。 所述注入锁定振荡器接收第一时钟信号并通过使所述第一时钟信号偏移来提供第二时钟信号。 所述发送装置接收输入信号并接收所述第二时钟信号作为时钟信号，所述发送装置基于所接收的定时信号发送输出信号。
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公开(公告)号：US07345605B2
公开(公告)日：2008-03-18
申请号：US10325097
申请日：2002-12-20
申请人： James E. Jaussi , Bryan K. Casper
发明人： James E. Jaussi , Bryan K. Casper
IPC分类号： H03M3/00
CPC分类号： H03M5/20
摘要： According to some embodiments, a circuit includes a current mirror to receive a multi-level current signal, and to generate a plurality of current signals substantially identical to the multi-level current signal. Such a circuit may also include a plurality of current comparison circuits, each of the plurality of current comparison circuits to receive a respective one of the plurality of generated current signals, to receive a respective reference current signal, and to generate a signal indicating a relationship between the received respective one of the plurality of generated current signals and the respective reference current signal.
摘要翻译： 根据一些实施例，电路包括电流镜以接收多电平电流信号，并且产生与多电平电流信号基本相同的多个电流信号。 这种电路还可以包括多个电流比较电路，多个电流比较电路中的每一个用于接收多个产生的电流信号中的相应一个，以接收相应的参考电流信号，并且产生指示关系的信号 在所接收的多个发生的电流信号中的相应一个信号和相应的参考电流信号之间。
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公开(公告)号：US07313181B2
公开(公告)日：2007-12-25
申请号：US10660415
申请日：2003-09-10
CPC分类号： H04L25/03038 , H03H21/0001 , H03H2021/0065 , H04L2025/03477
摘要： An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: h(t+1)= h(t)+μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{ x(t)}, where h(t) is the filter vector representing the filter taps of the FIR filter, x(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, μ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.
摘要翻译： 用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器：
h（t + 1 ）= h（t）+ mu [sgn {d（t-sgn {z（t）-Kd（t）sgn { x（t）}， 其中 h（t）是表示FIR滤波器的滤波器抽头的滤波器向量， x（t）是表示接收到的当前和过去样本的数据向量 数据x（t），d（t）是用于训练的期望数据，z（t）是FIR滤波器的输出，μ确定适配的存储器或窗口大小，K是考虑到的比例因子 通信信道，接收机和均衡器的实际限制。此外，提供了用于校准比例因子K的过程和电路结构。 -
公开(公告)号：US07019592B2
公开(公告)日：2006-03-28
申请号：US10987363
申请日：2004-11-12
申请人： James E. Jaussi
发明人： James E. Jaussi
IPC分类号： H03F3/45
CPC分类号： H03G1/0088 , H03F3/45183 , H03F2203/45466 , H03F2203/45641 , H03G1/0023
摘要： An amplifier includes multiple gain ranges. The gain range can be set by electrically adding or removing load devices.
摘要翻译： 放大器包括多个增益范围。 增益范围可以通过电加载或去除负载设备来设置。
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公开(公告)号：US06747490B1
公开(公告)日：2004-06-08
申请号：US10328205
申请日：2002-12-23
IPC分类号： H03K3289
CPC分类号： H04L25/028 , H03K3/356139 , H03K3/35625 , H04L25/0272 , H04L25/0292
摘要： According to some embodiments, a circuit provides a first set of one or more flip-flops to receive a low-swing differential clock, and a second set of one or more flip-flops to receive the low-swing differential clock. One of the one or more flip-flops of the first set is to generate a first CMOS-level sampling pulse for each cycle of the low-swing differential clock, and wherein one of the one or more flip-flops of the second set is to generate a second CMOS-level sampling pulse for each cycle of the low-swing differential clock.
摘要翻译： 根据一些实施例，电路提供第一组一个或多个触发器以接收低摆幅差分时钟，以及第二组一个或多个触发器来接收低摆幅差分时钟。 第一组的一个或多个触发器中的一个是为低摆动差分时钟的每个周期产生第一CMOS电平采样脉冲，并且其中第二组的一个或多个触发器中的一个是 以产生低回波差分时钟的每个周期的第二CMOS电平采样脉冲。
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公开(公告)号：US09654342B2
公开(公告)日：2017-05-16
申请号：US13995590
申请日：2011-09-30
CPC分类号： H04L41/0896 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more device-side data lanes and transceiver logic to receive a bandwidth configuration command. The transceiver logic may also configure a transmit bandwidth of the one or more device-side data lanes based on the bandwidth configuration command. Additionally, the transceiver logic can configure a receive bandwidth of the one or more device-side data lanes based on the bandwidth configuration command.
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