公开(公告)号：US07307323B2

公开(公告)日：2007-12-11

申请号：US11369409

申请日：2006-03-07

申请人： Hung Y. Ng ,  Haining S. Yang

发明人： Hung Y. Ng ,  Haining S. Yang

IPC分类号： H01L29/76

CPC分类号： H01L29/665 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823468 ,  H01L27/0629 ,  H01L29/6656

摘要： An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and determines the location of silicide formation within source and drain regions within the substrate at the base of the transistor gate stack. The liner also covers a resistor gate stack preventing silicide formation within or adjacent to the resistor gate stack.

摘要翻译： 覆盖晶体管栅极叠层的侧壁并且沿晶体管栅极堆叠的基极的衬底的一部分覆盖的耐蚀刻衬里。 衬垫防止在栅极堆叠的侧壁上形成硅化物，这可能产生电短路，并且确定在晶体管栅极堆叠的基极处的衬底内的源极和漏极区域内的硅化物形成的位置。 衬套还覆盖阻止在电阻器栅极叠层内或邻近电阻器栅叠层形成硅化物的电阻器栅极堆叠。

公开(公告)号：US08853746B2

公开(公告)日：2014-10-07

申请号：US11427495

申请日：2006-06-29

申请人： Xiangdong Chen ,  Thomas W. Dyer ,  Kenneth Settlemyer ,  Haining S. Yang

发明人： Xiangdong Chen ,  Thomas W. Dyer ,  Kenneth Settlemyer ,  Haining S. Yang

IPC分类号： H01L29/76 ,  H01L27/148 ,  H01L29/66 ,  H01L29/165 ,  H01L29/786 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84 ,  H01L29/04 ,  H01L29/10 ,  H01L21/762 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78684 ,  H01L29/78696

摘要： The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.

摘要翻译： 本发明涉及具有应力通道区域的改进的互补金属氧化物半导体（CMOS）器件。 具体地，每个改进的CMOS器件包括具有位于半导体器件结构中的沟道区的场效应晶体管（FET），其具有沿着第一组等效晶面中的一个取向的顶表面和沿着 第二，不同组的等效晶面。 这种附加表面可以通过晶体蚀刻容易地形成。 此外，具有固有压缩或拉伸应力的一个或多个应力层位于半导体器件结构的附加表面上，并且被布置和构造成将拉应力或压应力施加到FET的沟道区。 这种应力层可以通过具有与半导体器件结构不同的晶格常数的半导体材料的假晶生长来形成。

公开(公告)号：US08765558B2

公开(公告)日：2014-07-01

申请号：US13427237

申请日：2012-03-22

申请人： Kangguo Cheng ,  Haining S. Yang

发明人： Kangguo Cheng ,  Haining S. Yang

IPC分类号： H01L21/02

CPC分类号： H01L21/823878 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203

摘要： A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.

公开(公告)号：US08629506B2

公开(公告)日：2014-01-14

申请号：US12407011

申请日：2009-03-19

申请人： Kangguo Cheng ,  Haining S. Yang

发明人： Kangguo Cheng ,  Haining S. Yang

IPC分类号： H01L21/70

CPC分类号： H01L21/823878 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203

摘要： A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.

摘要翻译： CMOS结构和用于制造CMOS结构的方法包括位于半导体衬底内的位于第一极性的第一有源区上的第一栅极和位于不同于第一极性的第二极性的第二有源区上的第二栅极。 第一有源区和第二有源区被隔离区隔开。 第一栅极和第二栅极是共线的，面向端壁终止在隔离区上。 面对的端壁不具有相邻或邻接的间隔件，尽管第一栅极和第二栅极的侧壁都是。 可以使用顺序替换栅极方法来制造CMOS结构。

公开(公告)号：US08587062B2

公开(公告)日：2013-11-19

申请号：US11690975

申请日：2007-03-26

申请人： Jack A. Mandelman ,  Haining S. Yang

发明人： Jack A. Mandelman ,  Haining S. Yang

IPC分类号： H01L27/12

CPC分类号： H01L29/78615

摘要： A field effect transistor (FET) with an adjacent body contact, a SOI IC with circuits including the FETs and a method of fabricating the ICs. Device islands are formed in the silicon surface layer of a SOI wafer. Gates are defined on the wafer. Body contacts are formed in a perimeter conductive region adjacent to the gates. The body contacts may be either a silicide strap along the gate sidewall at one side of the FET or a separate contact separated from the gate by a dielectric stripe at one side of the FET. Separate contacts may be connected to a bias supply.

摘要翻译： 具有相邻体接触的场效应晶体管（FET），具有包括FET的电路的SOI IC和制造IC的方法。 器件岛形成在SOI晶片的硅表面层中。 盖子被定义在晶圆上。 主体触点形成在与栅极相邻的周边导电区域中。 主体触点可以是沿FET的一侧的栅极侧壁的硅化物带或通过FET一侧的介电条与栅极分开的单独触点。 单独的触点可能连接到偏置电源。

公开(公告)号：US08361704B2

公开(公告)日：2013-01-29

申请号：US12352051

申请日：2009-01-12

申请人： Matthew E. Colburn ,  Wai-kin Li ,  Haining S. Yang

发明人： Matthew E. Colburn ,  Wai-kin Li ,  Haining S. Yang

IPC分类号： G03F7/20

CPC分类号： G03F7/40 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： This invention provides a method for reducing tip-to-tip spacing between lines using a combination of photolithographic and copolymer self-assembling lithographic techniques. A mask layer is first formed over a substrate with a line structure. A trench opening of a width d is created in the mask layer. A layer of a self-assembling block copolymer is then applied over the mask layer. The block copolymer layer is annealed to form a single unit polymer block of a width or a diameter w which is smaller than d inside the trench opening. The single unit polymer block is selectively removed to form a single opening of a width or a diameter w inside the trench opening. An etch transfer process is performed using the single opening as a mask to form an opening in the line structure in the substrate.

摘要翻译： 本发明提供了使用光刻和共聚物自组装光刻技术的组合来减少线之间的尖端到尖端间隔的方法。 首先在具有线结构的衬底上形成掩模层。 在掩模层中形成宽度为d的沟槽开口。 然后将一层自组装嵌段共聚物施加在掩模层上。 对嵌段共聚物层进行退火以在沟槽开口内形成宽度或直径w小于d的单一单元聚合物嵌段。 选择性地去除单个单元聚合物嵌段以在沟槽开口内形成宽度或直径w的单个开口。 使用单个开口作为掩模进行蚀刻转印处理，以在基板中的线结构中形成开口。

公开(公告)号：US20120214301A1

公开(公告)日：2012-08-23

申请号：US13453165

申请日：2012-04-23

申请人： Deok-Kee Kim ,  Ahmet S. Ozcan ,  Haining S. Yang

发明人： Deok-Kee Kim ,  Ahmet S. Ozcan ,  Haining S. Yang

IPC分类号： H01L21/28

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.

摘要翻译： 电熔丝结构和方法具有阳极; 熔丝连接（熔丝连接的第一端连接到阳极）; 阴极（与第一端相对的熔断体的第二端连接到阴极）; 和熔丝链上的硅化物层。 硅化物层具有邻近阳极的第一硅化物区域和与阴极相邻的第二硅化物区域。 第二硅化物区域包括不包含在第一硅化物区域内的杂质。 此外，第一硅化物区域比第二硅化物区域薄。

公开(公告)号：US08093644B2

公开(公告)日：2012-01-10

申请号：US12350432

申请日：2009-01-08

申请人： Haining S. Yang

发明人： Haining S. Yang

IPC分类号： H01L21/00

CPC分类号： H01L51/0558 ,  B82Y10/00 ,  G11C13/025 ,  G11C16/0416 ,  G11C2213/17 ,  H01L21/28273 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1606 ,  H01L51/0048 ,  Y10S977/742 ,  Y10S977/939

摘要： A carbon nanotube based memory device comprises a set of three concentric carbon nanotubes having different diameters. The diameters of the three concentric carbon nanotubes are selected such that an inner carbon nanotube is semiconducting, and intershell electron transport occurs between adjacent carbon nanotubes. Source and drain contacts are made to the inner carbon nanotube, and a gate contact is made to the outer carbon nanotube. The carbon nanotube based memory device is programmed by storing electrons or holes in the middle carbon nanotube through intershell electron transport. Changes in conductance of the inner carbon nanotube due to the charge in the middle shell are detected to determine the charge state of the middle carbon nanotube. Thus, the carbon nanotube based memory device stores information in the middle carbon nanotube in the form of electrical charge.

摘要翻译： 一种基于碳纳米管的存储器件包括一组具有不同直径的三个同心碳纳米管。 选择三个同心碳纳米管的直径使得内部碳纳米管是半导体的，并且在相邻的碳纳米管之间发生壳内电子传递。 对内部碳纳米管进行源极和漏极接触，并对外部碳纳米管进行栅极接触。 基于碳纳米管的存储器件通过在壳碳纳米管中通过壳电子传输存储电子或空穴进行编程。 检测由于中间壳中的电荷导致的内部碳纳米管的电导率的变化，以确定中间碳纳米管的电荷状态。 因此，基于碳纳米管的存储装置以电荷的形式将信息存储在中间碳纳米管中。

公开(公告)号：US07973409B2

公开(公告)日：2011-07-05

申请号：US11625576

申请日：2007-01-22

申请人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

发明人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/76841 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.

摘要翻译： 本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。 更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地， 气隙。 与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。 此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

公开(公告)号：US07968910B2

公开(公告)日：2011-06-28

申请号：US12103301

申请日：2008-04-15

申请人： Xiangdong Chen ,  Thomas W. Dyer ,  Haining S. Yang

发明人： Xiangdong Chen ,  Thomas W. Dyer ,  Haining S. Yang

IPC分类号： H01L21/02 ,  H01L27/12

CPC分类号： H01L21/823807 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.

摘要翻译： 提供了制造互补应力半导体器件的方法，例如具有拉伸应力通道的NFET和具有压应力通道的PFET。 在这种方法中，可以在衬底的下面的半导体区域外延生长具有大于硅的晶格常数的第一半导体区域。 第一半导体区域可以与具有比硅的晶格常数小的晶格常数的第二半导体区域横向生长。 基本上由硅组成的层可以外延生长到第一和第二半导体区域的暴露的主表面上，之后可以形成覆盖外延生长的硅层的栅极。 可以去除与栅极相邻的第一和第二半导体区域的部分以形成凹部。 基本上由硅组成的区域可以在凹槽内生长以形成嵌入的硅区域。 然后可以在嵌入的硅区域中形成源区和漏区。 硅的晶格常数和下面的第一和第二区域的晶格常数之间的差异导致第一半导体区域上的拉伸应力硅和第二半导体区域上的压应力硅。