公开(公告)号：US07387925B2

公开(公告)日：2008-06-17

申请号：US11799261

申请日：2007-04-10

申请人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

发明人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/7841

摘要： A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

摘要翻译： 公开了一种用于压缩应变Ge层中的PFET器件的结构和方法。 这种器件的制造方法与标准CMOS技术兼容，并且具有完全可扩展性。 该处理包括超过50％Ge含量缓冲层，纯Ge层和SiGe顶层的选择性外延沉积。 承载在压缩应变Ge层中的制造掩埋沟道PMOS器件相对于类似的Si器件显示出优异的器件特性。

公开(公告)号：US07244958B2

公开(公告)日：2007-07-17

申请号：US10876155

申请日：2004-06-24

申请人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

发明人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

IPC分类号： H01L29/06 ,  H01L31/0328

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/7841

摘要： A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

公开(公告)号：US07183576B2

公开(公告)日：2007-02-27

申请号：US10775514

申请日：2004-02-10

申请人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

发明人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

IPC分类号： H01L29/16 ,  H01L29/737

CPC分类号： C23C16/325 ,  C23C16/32 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/12674

摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitakial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon

摘要翻译： 描述了一种用于在热壁，等温UHV-CVD系统中在多个基板上沉积单晶，硅碳和硅锗碳外延膜的方法和装置。 特别地，描述了在350℃至750℃的范围内的多晶片低温生长技术，用于在Si和SiGe膜中外延引入碳，其具有非常突然且明确限定的结，但没有任何相关的氧背景污染。 优选地，这些成膜SiC和SiGeC膜是原位掺杂的p型或n型，并且存在低浓度的碳<20 20 -3 -3， 生长的p型或n型掺杂物分布可以承受炉退火至850℃的温度和快速热退火温度至1000℃

公开(公告)号：US07173274B2

公开(公告)日：2007-02-06

申请号：US10953378

申请日：2004-09-29

申请人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

发明人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0339

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

摘要翻译： 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

公开(公告)号：US07145167B1

公开(公告)日：2006-12-05

申请号：US09936320

申请日：2000-03-11

申请人： Jack Oon Chu

发明人： Jack Oon Chu

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/0336 ,  H01L21/44

CPC分类号： H01L29/7782 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66431

摘要： A method and a layered heterostructure for forming high mobility Ge channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, and a channel structure of a compressively strained epitaxial Ge layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility for complementary MODFETs and MOSFETs. The invention overcomes the problem of a limited hole mobility due to alloy scattering for a p-channel device with only a single compressively strained SiGe channel layer. This invention further provides improvements in mobility and transconductance over deep submicron state-of-the art Si pMOSFETs in addition to having a broad temperature operation regime from above room temperature (425 K) down to cryogenic low temperatures (0.4 K) where at low temperatures even high device performances are achievable.

摘要翻译： 一种用于形成高迁移率Ge沟道场效应晶体管的方法和分层异质结构被描述为在半导体衬底上并入多个半导体层，以及具有较高势垒或更深限制量子阱的压缩应变外延Ge层的沟道结构， 对互补的MODFET和MOSFET具有极高的空穴迁移率。 本发明克服了由于仅具有单个压缩应变SiGe沟道层的p沟道器件的合金散射引起的有限空穴迁移率的问题。 本发明进一步提供了在深亚微米级的最先进的Si pMOSFETs的迁移率和跨导性方面的改进，以及从室温（425K）到低温低温（0.4K）的宽温度操作方案，其中在低温下 甚至可以实现高设备性能。

公开(公告)号：US06927414B2

公开(公告)日：2005-08-09

申请号：US10462933

申请日：2003-06-17

申请人： Qiqing Christine Ouyang ,  Jack Oon Chu

发明人： Qiqing Christine Ouyang ,  Jack Oon Chu

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/80 ,  H01L21/36

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/802 ,  Y10S438/933

摘要： A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

摘要翻译： 描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的应变横向沟道结构的方法，其在单晶半导体衬底上结合了漏极，主体和源极区域，其中在 晶体管的源极和主体，其中源极区域和沟道独立地相对于身体区域进行晶格应变。 本发明通过异质结和晶格应变来减少来自源极区的漏电流的问题，同时通过选择半导体材料和合金组成独立地允许沟道区域中的晶格应变增加迁移率。

公开(公告)号：US06890835B1

公开(公告)日：2005-05-10

申请号：US09692606

申请日：2000-10-19

申请人： Jack Oon Chu ,  David R. DiMilia ,  Lijuan Huang

发明人： Jack Oon Chu ,  David R. DiMilia ,  Lijuan Huang

IPC分类号： H01L21/331 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/338 ,  H01L21/762 ,  H01L27/12 ,  H01L29/161 ,  H01L29/737 ,  H01L29/778 ,  H01L29/786 ,  H01L29/812 ,  H01L29/861 ,  H01L31/10 ,  H01L21/30 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14 ,  C30B29/10 ,  H01L21/46

CPC分类号： H01L21/76256 ,  H01L21/2007

摘要： A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly seletive etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts of the SiGe/Si heterojunction diodes.

摘要翻译： 描述了在松散的SiGe绝缘体上（SGOI）上形成应变Si或SiGe的方法或Si异质结构上的SiGe的方法，该方法包括生长外延Si 1-y Ge层 半导体衬底，通过化学机械抛光的平滑表面，通过热处理将两个衬底粘合在一起，并通过使用SiGe本身作为蚀刻停止层的高精密蚀刻将SiGe层从一个衬底转移到另一衬底。 转移的SiGe层可以通过CMP平滑其上表面，用于外延沉积弛豫的Si 1-y Ge y Si，并且应变Si 1-y

公开(公告)号：US06750119B2

公开(公告)日：2004-06-15

申请号：US09838892

申请日：2001-04-20

申请人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

发明人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

IPC分类号： H01L2120

CPC分类号： C23C16/325 ,  C23C16/32 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/12674

摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon