公开(公告)号：US06839861B2

公开(公告)日：2005-01-04

申请号：US09918081

申请日：2001-07-30

申请人： Joseph Michael Hoke ,  Frank D. Ferraiolo ,  Tin-Chee Lo ,  John Michael Yarolin

发明人： Joseph Michael Hoke ,  Frank D. Ferraiolo ,  Tin-Chee Lo ,  John Michael Yarolin

IPC分类号： H04L7/00 ,  H04L7/033 ,  H04L25/14 ,  G06F1/04

CPC分类号： H04L7/0338 ,  H04L7/0008 ,  H04L25/14

摘要： An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.

摘要翻译： 本发明的一个示例性实施例是一种用于在多个并行数据线和时钟信号线之间在处理器之间传送数据的方法。 接收器处理器从发送器处理器接收数据和时钟信号。 在接收机处理器处，数据的一部分与发射的时钟信号相对准。 相位对准包括从延迟链中的多个数据相位中选择数据相位，然后调整所选择的数据相位以补偿舍入误差。 另外的实施例包括用于在多个并行数据线和时钟信号线之间在处理器之间传输数据的系统和存储介质。

公开(公告)号：US06025744A

公开(公告)日：2000-02-15

申请号：US62415

申请日：1998-04-17

申请人： Allan R. Bertolet ,  Albert M. Chu ,  Frank D. Ferraiolo ,  Samuel K. Weinstein

发明人： Allan R. Bertolet ,  Albert M. Chu ,  Frank D. Ferraiolo ,  Samuel K. Weinstein

IPC分类号： H03H11/26 ,  H03K5/00 ,  H03K5/1252 ,  H03K5/13

CPC分类号： H03K5/133 ,  H03K5/1252 ,  H03K2005/00058 ,  H03K2005/00156

摘要： A glitch free delay line multiplexing technique is described that includes an intermediate multiplexing system and an output multiplexer. The intermediate multiplexing system receives signals from a plurality of delay units and outputs a subset of delay signals that includes the signal presently selected, the signal presently selected with an additional delay, and the signal presently selected with one less delay. The intermediate multiplexing system receives a control word from a select mechanism in a non-time critical manner. The output multiplexer receives the least significant bits of the control word and outputs the selected signal.

摘要翻译： 描述了一种无毛刺延迟线复用技术，其包括中间复用系统和输出多路复用器。 中间复用系统从多个延迟单元接收信号并输出​​包括当前选择的信号的延迟信号的子集，当前选择的信号是附加的延迟，以及当前用一个较小延迟选择的信号。 中间复用系统以非时间关键的方式从选择机制接收控制字。 输出多路复用器接收控制字的最低有效位并输出所选择的信号。

公开(公告)号：US5968137A

公开(公告)日：1999-10-19

申请号：US906173

申请日：1997-08-04

申请人： Frank D. Ferraiolo ,  Don T. Gottstine ,  Jurgen Hass ,  Joseph B. Hanley ,  Thomas H. Hillock ,  Donald Jung

发明人： Frank D. Ferraiolo ,  Don T. Gottstine ,  Jurgen Hass ,  Joseph B. Hanley ,  Thomas H. Hillock ,  Donald Jung

IPC分类号： H04L12/26 ,  H04L29/06 ,  H03M7/30

CPC分类号： H04L43/50 ,  H04L12/2697 ,  H04L29/06 ,  H04L69/08 ,  H04L69/03

摘要： A method for testing protocol converters is presented, which permits the achievement of a test of all commands, independently of a corresponding test system. A modified protocol converter itself is used for the test. With the help of this method, a test for conversion of data structures can be carried out, of a slow protocol into the corresponding data structures of a fast protocol in the original speed.

摘要翻译： 提出了一种用于测试协议转换器的方法，它可以独立于相应的测试系统实现所有命令的测试。 修改后的协议转换器本身用于测试。 借助这种方法，可以将缓慢协议的数据结构转换测试以原始速度执行到快速协议的相应数据结构。

公开(公告)号：US5635869A

公开(公告)日：1997-06-03

申请号：US536222

申请日：1995-09-29

申请人： Frank D. Ferraiolo ,  John E. Gersbach ,  Ilya J. Novof ,  Edward J. Nowak

发明人： Frank D. Ferraiolo ,  John E. Gersbach ,  Ilya J. Novof ,  Edward J. Nowak

IPC分类号： G05F3/26 ,  G05F1/10

CPC分类号： G05F3/262

摘要： A constant-current generator circuit includes an output circuit and a control circuit, with the control circuit producing a control voltage to define a reference current through the output circuit. An important feature is that the control circuit uses a pair of transistors having different threshold voltages in generating the control voltage. The circuit is formed using CMOS technology, and the difference in threshold voltage may be produced by doping the polysilicon gate of an N-channel or P-channel field effect transistor. The step of doping to produce the change in threshold voltage is compatible with the standard processing for the CMOS device. In a preferred embodiment, the control circuit uses two pairs of control transistors, each pair having differing thresholds. One pair is P-channel and the other N-channel. These pairs are in parallel, the P-channel pair connected to the positive supply and the N-channel pair to the negative supply or ground. Each pair is connected in a cascode arrangement, producing two control voltages for two symmetrical output transistors in the output circuit, one N-channel and one P-channel.

摘要翻译： 恒流发生器电路包括输出电路和控制电路，控制电路产生控制电压以限定通过输出电路的参考电流。 一个重要的特征是控制电路在产生控制电压时使用具有不同阈值电压的一对晶体管。 该电路使用CMOS技术形成，并且阈值电压的差异可以通过掺杂N沟道或P沟道场效应晶体管的多晶硅栅极产生。 掺杂产生阈值电压变化的步骤与CMOS器件的标准处理兼容。 在优选实施例中，控制电路使用两对控制晶体管，每对控制晶体管具有不同的阈值。 一对是P通道和另一个N通道。 这些对并联，P沟道对连接到正电源，N沟道对连接到负电源或地。 每对以串联布置连接，为输出电路中的两个对称输出晶体管产生两个控制电压，一个N沟道和一个P沟道。

公开(公告)号：US5598442A

公开(公告)日：1997-01-28

申请号：US261522

申请日：1994-06-17

申请人： Thomas A. Gregg ,  Robert S. Capowski ,  Daniel F. Casper ,  Frank D. Ferraiolo

发明人： Thomas A. Gregg ,  Robert S. Capowski ,  Daniel F. Casper ,  Frank D. Ferraiolo

IPC分类号： G06F13/42 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L7/04 ,  H04L12/56 ,  H04L25/14 ,  H04L25/49 ,  H04L29/06

CPC分类号： H04L29/06 ,  G06F13/4278 ,  H04L25/14 ,  H04L25/4908 ,  H04L7/041 ,  H04L2007/045 ,  H04L69/14 ,  H04L7/0008

摘要： A self-timed interface (STI) links two physically separated systems or nodes. A transmit state machine forms each word in a serial bit stream into a plurality of bytes and generates idle and data character sequences. Each byte is separately encoded in a run-length-limited code, along with its idle and data character sequences. Each of the plurality of bytes is transmitted on a separate conducting line along with a transmit clock signal that is also transmitted on a separate line. At the receiver, the data stream on each line is separately phase aligned with the clock, and bit aligned.

摘要翻译： 自定义接口（STI）链接两个物理上分离的系统或节点。 发送状态机将串行比特流中的每个单词形成多个字节，并生成空闲和数据字符序列。 每个字节分别以游程长度限制的代码及其空闲和数据字符序列编码。 多个字节中的每一个与分离的线路上发送的发送时钟信号一起在单独的导线上发送。 在接收机上，每行上的数据流与时钟分开相位对齐，并且位对齐。

公开(公告)号：US5522088A

公开(公告)日：1996-05-28

申请号：US261641

申请日：1994-06-17

申请人： Marten J. Halma ,  Robert S. Capowski ,  Daniel F. Casper ,  Frank D. Ferraiolo ,  Martin W. Sachs

发明人： Marten J. Halma ,  Robert S. Capowski ,  Daniel F. Casper ,  Frank D. Ferraiolo ,  Martin W. Sachs

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/405

摘要： A shared channel subsystem has an input-output element for coupling each of a plurality of input-output controllers to each of a plurality of processor nodes by means of a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal, providing a cost effective, modular input/output element.

摘要翻译： 共享信道子系统具有用于通过自定义接口（STI）将多个输入 - 输出控制器中的每一个耦合到多个处理器节点中的每一个的输入 - 输出元件，其中时钟信号将位串行数据时钟 并行的导电总线，并且时钟信号在总线的单独线路上传输。 总线上每条线上的接收数据与时钟信号单独相位对齐，提供了一个经济有效的模块化输入/输出元件。

公开(公告)号：US4901076A

公开(公告)日：1990-02-13

申请号：US114178

申请日：1987-10-29

申请人： Haluk O. Askin ,  Frank D. Ferraiolo

发明人： Haluk O. Askin ,  Frank D. Ferraiolo

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A circuit for converting a multi-bit data signal from a first format to a second format. The circuit includes an input for receiving the multi-bit data signal in a first format, an output for providing the multi-bit data signal in a second format, and a ring counter having a number of stages for providing, in sequential order, stage output signals. A format conversion device connected between the input and the output has a number of latches with each latch being connected to the input for simultaneously receiving data bits of the multi-bit data signal in the first format. A control circuit is provided for controlling the latching of selected data bits in each of the latches, and a transmission circuit is provided between the latches and the output for transmitting the bits latched in the latches to the output responsive to the stage output signals of the ring counter, thereby placing the multi-bit data signal in the second format.

公开(公告)号：US08862944B2

公开(公告)日：2014-10-14

申请号：US12822508

申请日：2010-06-24

申请人： John S. Dodson ,  Frank D. Ferraiolo ,  Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Kenneth L. Wright ,  Lisa C. Gower

发明人： John S. Dodson ,  Frank D. Ferraiolo ,  Michele M. Franceschini ,  Kevin C. Gower ,  Ashish Jagmohan ,  Luis A. Lastras-Montano ,  Kenneth L. Wright

IPC分类号： G06F11/00 ,  G06F11/20 ,  G06F11/10 ,  H04L1/00

CPC分类号： G06F11/10 ,  G06F11/2005 ,  H04L1/0061 ,  H04L2001/0096

摘要： Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links. An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.

摘要翻译： 隔离传输介质中的故障链路，包括包括通过具有多个传输链路的多链路传输介质接收原子数据单元的方法。 检测到错误状况，并且确定错误状况被隔离到单个传输链路。 在由定时器指定的间隔内，确定单个传输链路是否已经被隔离为先前被隔离的传输链路指定的次数。 如果单个传输链路在由定时器指定的间隔内已经被隔离为失败的传输链路指定的次数，则：将单个传输链路识别为有故障的传输链路; 重置定时器; 并输出单个传输链路的标识符。

公开(公告)号：US20140032799A1

公开(公告)日：2014-01-30

申请号：US13561446

申请日：2012-07-30

申请人： Timothy O. Dickson ,  Daniel M. Dreps ,  Frank D. Ferraiolo ,  Douglas J. Joseph

发明人： Timothy O. Dickson ,  Daniel M. Dreps ,  Frank D. Ferraiolo ,  Douglas J. Joseph

IPC分类号： G06F13/00

CPC分类号： G06F15/17318 ,  G06F9/00 ,  G06F11/3058 ,  G06F13/00 ,  G06F13/1673 ,  G06F13/24 ,  G06F13/4217 ,  G06F13/4282 ,  G06F15/803 ,  G06F19/00 ,  H04B1/38 ,  H04L12/56 ,  Y02D10/14 ,  Y02D10/151

摘要： A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.

摘要翻译： 可校准通信链路包括多条平行线。 由自动机制确定的动态变量和/或可中断间隔进行校准。 校准优选地响应于由可执行软件过程产生的命令来启动，该指令响应于可能的即将发生的需求的检测而启动校准，如由温度变化，校准参数漂移，错误率等指示的。也优选地根据 可能的最小的设备功能中断，如低活动水平所示。 此外，在一个方面，可以临时暂停校准以发送数据，然后恢复。

公开(公告)号：US08050174B2

公开(公告)日：2011-11-01

申请号：US12886404

申请日：2010-09-20

申请人： Wiren D. Becker ,  Daniel M. Dreps ,  Frank D. Ferraiolo ,  Anand Haridass ,  Robert J. Reese

发明人： Wiren D. Becker ,  Daniel M. Dreps ,  Frank D. Ferraiolo ,  Anand Haridass ,  Robert J. Reese

IPC分类号： G01R31/08

CPC分类号： H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.